llvm-project/llvm/test/MC
Simon Tatham 286e1d2c2d [ARM] Set up infrastructure for MVE vector instructions.
This commit prepares the way to start adding the main collection of
MVE instructions, which operate on the 128-bit vector registers.

The most obvious thing that's needed, and the simplest, is to add the
MQPR register class, which is like the existing QPR except that it has
fewer registers in it.

The more complicated part: MVE defines a system of vector predication,
in which instructions operating on 128-bit vector registers can be
constrained to operate on only a subset of the lanes, using a system
of prefix instructions similar to the existing Thumb IT, in that you
have one prefix instruction which designates up to 4 following
instructions as subject to predication, and within that sequence, the
predicate can be inverted by means of T/E suffixes ('Then' / 'Else').

To support instructions of this type, we've added two new Tablegen
classes `vpred_n` and `vpred_r` for standard clusters of MC operands
to add to a predicated instruction. Both include a flag indicating how
the instruction is predicated at all (options are T, E and 'not
predicated'), and an input register field for the register controlling
the set of active lanes. They differ from each other in that `vpred_r`
also includes an input operand for the previous value of the output
register, for instructions that leave inactive lanes unchanged.
`vpred_n` lacks that extra operand; it will be used for instructions
that don't preserve inactive lanes in their output register (either
because inactive lanes are zeroed, as the MVE load instructions do, or
because the output register isn't a vector at all).

This commit also adds the family of prefix instructions themselves
(VPT / VPST), and all the machinery needed to work with them in
assembly and disassembly (e.g. generating the 't' and 'e' mnemonic
suffixes on disassembled instructions within a predicated block)

I've added a couple of demo instructions that derive from the new
Tablegen base classes and use those two operand clusters. The bulk of
the vector instructions will come in followup commits small enough to
be manageable. (One exception is that I've added the full version of
`isMnemonicVPTPredicable` in the AsmParser, because it seemed
pointless to carefully split it up.)

Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62669

llvm-svn: 363258
2019-06-13 13:11:13 +00:00
..
AArch64 [AArch64][AsmParser] error on unexpected SVE predicate type suffix 2019-06-07 08:46:56 +00:00
AMDGPU [AMDGPU][MC] Enabled constant expressions as operands of s_getreg/s_setreg 2019-06-13 12:46:37 +00:00
ARM [ARM] Set up infrastructure for MVE vector instructions. 2019-06-13 13:11:13 +00:00
AVR Extend the DWARFExpression address handling to support 16-bit addresses 2019-06-01 09:18:26 +00:00
AsmParser [llvm-readobj] Change -t to --symbols in tests. NFC 2019-05-01 09:28:24 +00:00
BPF bpf: disassembler support for XADD under sub-register mode 2019-02-28 19:22:34 +00:00
COFF [codeview] Revert inline line table change of r362264 2019-05-31 22:55:03 +00:00
Disassembler [ARM] Set up infrastructure for MVE vector instructions. 2019-06-13 13:11:13 +00:00
ELF [MC][ELF] Don't create relocations with section symbols for STB_LOCAL ifunc 2019-06-07 03:47:22 +00:00
Hexagon [llvm-objdump] - Print relocation record in a GNU format. 2019-05-07 13:14:18 +00:00
Lanai
MSP430 [llvm-readobj] Change -t to --symbols in tests. NFC 2019-05-01 09:28:24 +00:00
MachO Fix typo in r361251. 2019-05-21 13:23:32 +00:00
Mips [Mips] Add s.d instruction alias for Mips1 2019-06-12 17:52:05 +00:00
PowerPC [PPC64] Update LocalEntry from assigned symbols 2019-05-21 10:41:25 +00:00
RISCV [RISCV] Support assembling TLS LA pseudo instructions 2019-05-23 14:46:27 +00:00
Sparc [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
SystemZ [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
WebAssembly [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
X86 [X86] Add VP2INTERSECT instructions 2019-05-31 02:50:41 +00:00