forked from OSchip/llvm-project
2f2e3c4737
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. llvm-svn: 142670 |
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ARMAsmLexer.cpp | ||
ARMAsmParser.cpp | ||
CMakeLists.txt | ||
Makefile |