forked from OSchip/llvm-project
9eb3cc10b2
Summary: This commit adds the predicated MVE intrinsics for the same set of unary operations that I added in their unpredicated forms in * D74333 (vrint) * D74334 (vrev) * D74335 (vclz, vcls) * D74336 (vmovl) * D74337 (vmovn) but since the predicated versions are a lot more similar to each other, I've kept them all together in a single big patch. Everything here is done in the standard way we've been doing other predicated operations: an IR intrinsic called `@llvm.arm.mve.foo.predicated` and some isel rules that match that alongside whatever they accept for the unpredicated version of the same instruction. In order to write the isel rules conveniently, I've refactored the existing isel rules for the affected instructions into multiclasses parametrised by a vector-type class, in the usual way. All those refactorings are intended to leave the existing isel rules unchanged: the only difference should be that new ones for the predicated intrinsics are introduced. The only tiny infrastructure change I needed in this commit was to change the implementation of `IntrinsicMX` in `arm_mve_defs.td` so that the records it defines are anonymous rather than named (and use `NameOverride` to set the output intrinsic name), which allows me to call it twice in two multiclasses with the same `NAME` without a tablegen-time error. Reviewers: dmgreen, MarkMurrayARM, miyuki, ostannard Reviewed By: MarkMurrayARM Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D75165 |
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| Hexagon | ||
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| Lanai | ||
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