llvm-project/llvm/lib/Target/RISCV/Utils
Pengxuan Zheng 85aff8a4e4 [RISCV] Update debug scratch register names
Summary:
The RISC-V debug register was named dscratch in a previous draft of the RISC-V
debug mode spec. The number of registers has been increased to 2 in the latest
ratified version of the debug mode spec and the registers were named dscratch0
and dscratch1. We still support using the old register name "dscratch", but it
would be disassembled as "dscratch0" with this change.

Reviewers: apazos, asb, lenary, luismarques

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78764
2020-05-05 08:46:07 -07:00
..
CMakeLists.txt [cmake] Explicitly mark libraries defined in lib/ as "Component Libraries" 2019-11-21 10:48:08 -08:00
LLVMBuild.txt
RISCVBaseInfo.cpp [RISCV] Support ABI checking with per function target-features 2020-01-22 08:12:28 -08:00
RISCVBaseInfo.h [RISCV] Update debug scratch register names 2020-05-05 08:46:07 -07:00
RISCVMatInt.cpp [RISCV] Avoid signed integer overflow UB in RISCVMatInt::generateInstSeq 2019-07-18 04:02:58 +00:00
RISCVMatInt.h [RISCV] Prevent re-ordering some adds after shifts 2019-06-18 20:38:08 +00:00