forked from OSchip/llvm-project
149 lines
4.5 KiB
C
149 lines
4.5 KiB
C
// REQUIRES: powerpc-registered-target
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// RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
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// RUN: -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \
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// RUN: -o - | FileCheck %s
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#include <altivec.h>
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vector signed char vsca;
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vector unsigned char vuca, vucb, vucc;
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vector unsigned short vusa, vusb, vusc;
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vector unsigned int vuia, vuib, vuic;
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vector unsigned long long vulla, vullb, vullc;
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vector unsigned __int128 vui128a, vui128b, vui128c;
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unsigned int uia;
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vector unsigned long long test_vpdepd(void) {
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// CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64>
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// CHECK-NEXT: ret <2 x i64>
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return vec_pdep(vulla, vullb);
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}
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vector unsigned long long test_vpextd(void) {
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// CHECK: @llvm.ppc.altivec.vpextd(<2 x i64>
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// CHECK-NEXT: ret <2 x i64>
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return vec_pext(vulla, vullb);
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}
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vector unsigned long long test_vcfuged(void) {
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// CHECK: @llvm.ppc.altivec.vcfuged(<2 x i64>
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// CHECK-NEXT: ret <2 x i64>
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return vec_cfuge(vulla, vullb);
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}
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unsigned long long test_vgnb_1(void) {
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// CHECK: @llvm.ppc.altivec.vgnb(<1 x i128> %{{.+}}, i32 2)
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// CHECK-NEXT: ret i64
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return vec_gnb(vui128a, 2);
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}
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unsigned long long test_vgnb_2(void) {
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// CHECK: @llvm.ppc.altivec.vgnb(<1 x i128> %{{.+}}, i32 7)
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// CHECK-NEXT: ret i64
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return vec_gnb(vui128a, 7);
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}
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unsigned long long test_vgnb_3(void) {
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// CHECK: @llvm.ppc.altivec.vgnb(<1 x i128> %{{.+}}, i32 5)
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// CHECK-NEXT: ret i64
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return vec_gnb(vui128a, 5);
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}
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vector unsigned char test_xxeval_uc(void) {
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// CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 0)
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// CHECK: ret <16 x i8>
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return vec_ternarylogic(vuca, vucb, vucc, 0);
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}
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vector unsigned short test_xxeval_us(void) {
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// CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 255)
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// CHECK: ret <8 x i16>
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return vec_ternarylogic(vusa, vusb, vusc, 255);
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}
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vector unsigned int test_xxeval_ui(void) {
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// CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 150)
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// CHECK: ret <4 x i32>
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return vec_ternarylogic(vuia, vuib, vuic, 150);
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}
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vector unsigned long long test_xxeval_ull(void) {
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// CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 1)
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// CHECK: ret <2 x i64>
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return vec_ternarylogic(vulla, vullb, vullc, 1);
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}
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vector unsigned __int128 test_xxeval_ui128(void) {
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// CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 246)
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// CHECK: ret <1 x i128>
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return vec_ternarylogic(vui128a, vui128b, vui128c, 246);
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}
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vector unsigned char test_xxgenpcvbm(void) {
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// CHECK: @llvm.ppc.vsx.xxgenpcvbm(<16 x i8> %{{.+}}, i32
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// CHECK-NEXT: ret <16 x i8>
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return vec_genpcvm(vuca, 0);
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}
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vector unsigned short test_xxgenpcvhm(void) {
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// CHECK: @llvm.ppc.vsx.xxgenpcvhm(<8 x i16> %{{.+}}, i32
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// CHECK-NEXT: ret <8 x i16>
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return vec_genpcvm(vusa, 0);
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}
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vector unsigned int test_xxgenpcvwm(void) {
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// CHECK: @llvm.ppc.vsx.xxgenpcvwm(<4 x i32> %{{.+}}, i32
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// CHECK-NEXT: ret <4 x i32>
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return vec_genpcvm(vuia, 0);
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}
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vector unsigned long long test_xxgenpcvdm(void) {
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// CHECK: @llvm.ppc.vsx.xxgenpcvdm(<2 x i64> %{{.+}}, i32
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// CHECK-NEXT: ret <2 x i64>
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return vec_genpcvm(vulla, 0);
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}
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vector signed char test_vec_vclrl_sc(void) {
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// CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8>
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// CHECK-BE-NEXT: ret <16 x i8>
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// CHECK-LE: @llvm.ppc.altivec.vclrrb(<16 x i8>
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// CHECK-LE-NEXT: ret <16 x i8>
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return vec_clrl(vsca, uia);
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}
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vector unsigned char test_vec_clrl_uc(void) {
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// CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8>
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// CHECK-BE-NEXT: ret <16 x i8>
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// CHECK-LE: @llvm.ppc.altivec.vclrrb(<16 x i8>
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// CHECK-LE-NEXT: ret <16 x i8>
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return vec_clrl(vuca, uia);
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}
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vector signed char test_vec_vclrr_sc(void) {
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// CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8>
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// CHECK-BE-NEXT: ret <16 x i8>
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// CHECK-LE: @llvm.ppc.altivec.vclrlb(<16 x i8>
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// CHECK-LE-NEXT: ret <16 x i8>
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return vec_clrr(vsca, uia);
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}
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vector unsigned char test_vec_clrr_uc(void) {
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// CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8>
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// CHECK-BE-NEXT: ret <16 x i8>
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// CHECK-LE: @llvm.ppc.altivec.vclrlb(<16 x i8>
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// CHECK-LE-NEXT: ret <16 x i8>
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return vec_clrr(vuca, uia);
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}
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vector unsigned long long test_vclzdm(void) {
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// CHECK: @llvm.ppc.altivec.vclzdm(<2 x i64>
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// CHECK-NEXT: ret <2 x i64>
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return vec_cntlzm(vulla, vullb);
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}
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vector unsigned long long test_vctzdm(void) {
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// CHECK: @llvm.ppc.altivec.vctzdm(<2 x i64>
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// CHECK-NEXT: ret <2 x i64>
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return vec_cnttzm(vulla, vullb);
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}
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