forked from OSchip/llvm-project
1693 lines
120 KiB
LLVM
1693 lines
120 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=legalizer -o - %s | FileCheck -check-prefix=UNPACKED %s
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=legalizer -o - %s | FileCheck -check-prefix=PACKED %s
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define amdgpu_ps half @image_load_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
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; UNPACKED-LABEL: name: image_load_f16
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; UNPACKED: bb.1 (%ir-block.0):
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; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
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; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
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; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
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; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
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; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
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; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
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; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
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; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
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; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
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; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
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; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
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; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
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; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
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; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s16) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
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; UNPACKED: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AMDGPU_INTRIN_IMAGE_LOAD]](s16)
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; UNPACKED: $vgpr0 = COPY [[ANYEXT]](s32)
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; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
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; PACKED-LABEL: name: image_load_f16
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; PACKED: bb.1 (%ir-block.0):
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; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
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; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
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; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
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; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
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; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
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; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
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; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
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; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
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; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
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; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
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; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
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; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
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; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
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; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s16) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
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; PACKED: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AMDGPU_INTRIN_IMAGE_LOAD]](s16)
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; PACKED: $vgpr0 = COPY [[ANYEXT]](s32)
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; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
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%tex = call half @llvm.amdgcn.image.load.2d.f16.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
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ret half %tex
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}
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define amdgpu_ps <2 x half> @image_load_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
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; UNPACKED-LABEL: name: image_load_v2f16
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; UNPACKED: bb.1 (%ir-block.0):
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; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
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; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
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; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
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; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
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; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
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; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
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; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
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; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
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; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
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; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
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; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
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; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
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; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
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; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
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; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
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; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
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; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
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; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
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; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
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; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
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; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
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; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
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; UNPACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
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; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
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; PACKED-LABEL: name: image_load_v2f16
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; PACKED: bb.1 (%ir-block.0):
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; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
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; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
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; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
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; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
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; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
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; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
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; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
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; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
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; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
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; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
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; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
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; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
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; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
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; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
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; PACKED: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)
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; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
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%tex = call <2 x half> @llvm.amdgcn.image.load.2d.v2f16.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
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ret <2 x half> %tex
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}
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define amdgpu_ps <3 x half> @image_load_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
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; UNPACKED-LABEL: name: image_load_v3f16
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; UNPACKED: bb.1 (%ir-block.0):
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; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
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; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
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; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
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; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
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; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
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; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
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; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
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; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
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; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
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; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
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; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
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; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
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; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
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; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
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; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
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; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
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; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
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; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
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; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
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; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
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; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
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; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
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; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
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; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
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; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
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; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
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; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
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; UNPACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
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; UNPACKED: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
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; UNPACKED: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
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; UNPACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
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; UNPACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
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; UNPACKED: [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
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; UNPACKED: $vgpr0 = COPY [[EXTRACT1]](<2 x s16>)
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; UNPACKED: $vgpr1 = COPY [[EXTRACT2]](<2 x s16>)
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; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
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; PACKED-LABEL: name: image_load_v3f16
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; PACKED: bb.1 (%ir-block.0):
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; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
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; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
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; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
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; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
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; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
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; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
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; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
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; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
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; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
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; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
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; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
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; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
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; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
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; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
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; PACKED: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s16>)
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; PACKED: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
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; PACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[UV1]](<2 x s16>), [[DEF]](<2 x s16>)
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; PACKED: [[UV2:%[0-9]+]]:_(<3 x s16>), [[UV3:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
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; PACKED: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
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; PACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[UV2]](<3 x s16>), 0
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; PACKED: [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
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; PACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
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; PACKED: $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
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; PACKED: $vgpr1 = COPY [[EXTRACT1]](<2 x s16>)
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; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
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%tex = call <3 x half> @llvm.amdgcn.image.load.2d.v3f16.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
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ret <3 x half> %tex
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}
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define amdgpu_ps <4 x half> @image_load_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
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; UNPACKED-LABEL: name: image_load_v4f16
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; UNPACKED: bb.1 (%ir-block.0):
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; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
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; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
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; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
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; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
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; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
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; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
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; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
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; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
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; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
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; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
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; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
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; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
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; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
|
|
; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
|
|
; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
|
|
; UNPACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
|
|
; UNPACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C]]
|
|
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
|
|
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
|
|
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
|
|
; UNPACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; UNPACKED: $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
; PACKED-LABEL: name: image_load_v4f16
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
|
|
; PACKED: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s16>)
|
|
; PACKED: $vgpr0 = COPY [[UV]](<2 x s16>)
|
|
; PACKED: $vgpr1 = COPY [[UV1]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
%tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
|
ret <4 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps half @image_load_tfe_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_tfe_f16
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; UNPACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; UNPACKED: $vgpr0 = COPY [[COPY10]](s32)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
|
|
; PACKED-LABEL: name: image_load_tfe_f16
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; PACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; PACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; PACKED: $vgpr0 = COPY [[COPY10]](s32)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
|
|
%res = call { half, i32 } @llvm.amdgcn.image.load.2d.sl_f16i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
|
%tex = extractvalue { half, i32 } %res, 0
|
|
%tfe = extractvalue { half, i32 } %res, 1
|
|
store i32 %tfe, i32 addrspace(1)* undef
|
|
ret half %tex
|
|
}
|
|
|
|
define amdgpu_ps <2 x half> @image_load_tfe_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_tfe_v2f16
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
|
|
; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; UNPACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
|
|
; PACKED-LABEL: name: image_load_tfe_v2f16
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
|
|
; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; PACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
|
|
; PACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; PACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
|
|
%res = call { <2 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v2f16i32s.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
|
%tex = extractvalue { <2 x half>, i32 } %res, 0
|
|
%tfe = extractvalue { <2 x half>, i32 } %res, 1
|
|
store i32 %tfe, i32 addrspace(1)* undef
|
|
ret <2 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps <3 x half> @image_load_tfe_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_tfe_v3f16
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
|
|
; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
|
|
; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
|
|
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
|
|
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
|
|
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
|
|
; UNPACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
|
|
; UNPACKED: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
|
|
; UNPACKED: G_STORE [[UV3]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; UNPACKED: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0
|
|
; UNPACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
|
|
; UNPACKED: [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
|
|
; UNPACKED: $vgpr0 = COPY [[EXTRACT1]](<2 x s16>)
|
|
; UNPACKED: $vgpr1 = COPY [[EXTRACT2]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
; PACKED-LABEL: name: image_load_tfe_v3f16
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
|
|
; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
|
|
; PACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
|
|
; PACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV1]](s32)
|
|
; PACKED: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[DEF1]](<2 x s16>)
|
|
; PACKED: [[UV3:%[0-9]+]]:_(<3 x s16>), [[UV4:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
|
|
; PACKED: G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; PACKED: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[UV3]](<3 x s16>), 0
|
|
; PACKED: [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
|
|
; PACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
|
|
; PACKED: $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
|
|
; PACKED: $vgpr1 = COPY [[EXTRACT1]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
%res = call { <3 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f16i32s.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
|
%tex = extractvalue { <3 x half>, i32 } %res, 0
|
|
%tfe = extractvalue { <3 x half>, i32 } %res, 1
|
|
store i32 %tfe, i32 addrspace(1)* undef
|
|
ret <3 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps <4 x half> @image_load_tfe_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_tfe_v4f16
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
|
|
; UNPACKED: G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
|
|
; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
|
|
; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
|
|
; UNPACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
|
|
; UNPACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C]]
|
|
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
|
|
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
|
|
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
|
|
; UNPACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; UNPACKED: $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
; PACKED-LABEL: name: image_load_tfe_v4f16
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
|
|
; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
|
|
; PACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
|
|
; PACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV1]](s32)
|
|
; PACKED: G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; PACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; PACKED: $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
%res = call { <4 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f16i32s.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
|
%tex = extractvalue { <4 x half>, i32 } %res, 0
|
|
%tfe = extractvalue { <4 x half>, i32 } %res, 1
|
|
store i32 %tfe, i32 addrspace(1)* undef
|
|
ret <4 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps half @image_load_f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_f16_dmask_0000
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
|
; UNPACKED: $vgpr0 = COPY [[DEF]](s32)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
|
|
; PACKED-LABEL: name: image_load_f16_dmask_0000
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
|
; PACKED: $vgpr0 = COPY [[DEF]](s32)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
|
|
%tex = call half @llvm.amdgcn.image.load.2d.f16.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
|
ret half %tex
|
|
}
|
|
|
|
define amdgpu_ps <2 x half> @image_load_v2f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_v2f16_dmask_1000
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
|
|
; PACKED-LABEL: name: image_load_v2f16_dmask_1000
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; PACKED: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
|
|
%tex = call <2 x half> @llvm.amdgcn.image.load.2d.v2f16.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
|
ret <2 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps <2 x half> @image_load_v2f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_v2f16_dmask_0000
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
|
|
; UNPACKED: $vgpr0 = COPY [[DEF]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
|
|
; PACKED-LABEL: name: image_load_v2f16_dmask_0000
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: $vgpr0 = COPY [[DEF]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
|
|
%tex = call <2 x half> @llvm.amdgcn.image.load.2d.v2f16.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
|
ret <2 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps <3 x half> @image_load_v3f16_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_v3f16_dmask_1100
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
|
|
; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
|
|
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]
|
|
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
|
|
; UNPACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
|
|
; UNPACKED: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
|
|
; UNPACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
|
|
; UNPACKED: [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
|
|
; UNPACKED: $vgpr0 = COPY [[EXTRACT1]](<2 x s16>)
|
|
; UNPACKED: $vgpr1 = COPY [[EXTRACT2]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
; PACKED-LABEL: name: image_load_v3f16_dmask_1100
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
|
|
; PACKED: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>)
|
|
; PACKED: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
|
|
; PACKED: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[UV]](<3 x s16>), 0
|
|
; PACKED: [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
|
|
; PACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
|
|
; PACKED: $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
|
|
; PACKED: $vgpr1 = COPY [[EXTRACT1]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
%tex = call <3 x half> @llvm.amdgcn.image.load.2d.v3f16.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
|
ret <3 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps <3 x half> @image_load_v3f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_v3f16_dmask_1000
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C1]], [[SHL]]
|
|
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
|
|
; UNPACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
|
|
; UNPACKED: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
|
|
; UNPACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
|
|
; UNPACKED: [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
|
|
; UNPACKED: $vgpr0 = COPY [[EXTRACT1]](<2 x s16>)
|
|
; UNPACKED: $vgpr1 = COPY [[EXTRACT2]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
; PACKED-LABEL: name: image_load_v3f16_dmask_1000
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; PACKED: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>)
|
|
; PACKED: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
|
|
; PACKED: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[UV]](<3 x s16>), 0
|
|
; PACKED: [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
|
|
; PACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
|
|
; PACKED: $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
|
|
; PACKED: $vgpr1 = COPY [[EXTRACT1]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
%tex = call <3 x half> @llvm.amdgcn.image.load.2d.v3f16.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
|
ret <3 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps <3 x half> @image_load_v3f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_v3f16_dmask_0000
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[DEF]](<4 x s16>), 0
|
|
; UNPACKED: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0
|
|
; UNPACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
|
|
; UNPACKED: [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
|
|
; UNPACKED: $vgpr0 = COPY [[EXTRACT1]](<2 x s16>)
|
|
; UNPACKED: $vgpr1 = COPY [[EXTRACT2]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
; PACKED-LABEL: name: image_load_v3f16_dmask_0000
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[DEF]](<4 x s16>), 0
|
|
; PACKED: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0
|
|
; PACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
|
|
; PACKED: [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
|
|
; PACKED: $vgpr0 = COPY [[EXTRACT1]](<2 x s16>)
|
|
; PACKED: $vgpr1 = COPY [[EXTRACT2]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
%tex = call <3 x half> @llvm.amdgcn.image.load.2d.v3f16.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
|
ret <3 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps <4 x half> @image_load_v4f16_dmask_1110(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_v4f16_dmask_1110
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
|
|
; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
|
|
; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
|
|
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
|
|
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
|
|
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
|
|
; UNPACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; UNPACKED: $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
; PACKED-LABEL: name: image_load_v4f16_dmask_1110
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
|
|
; PACKED: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s16>)
|
|
; PACKED: $vgpr0 = COPY [[UV]](<2 x s16>)
|
|
; PACKED: $vgpr1 = COPY [[UV1]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
%tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
|
ret <4 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps <4 x half> @image_load_v4f16_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_v4f16_dmask_1100
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
|
|
; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
|
|
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]
|
|
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
|
|
; UNPACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; UNPACKED: $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
; PACKED-LABEL: name: image_load_v4f16_dmask_1100
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
|
|
; PACKED: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)
|
|
; PACKED: $vgpr1 = COPY [[DEF]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
%tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
|
ret <4 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps <4 x half> @image_load_v4f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_v4f16_dmask_1000
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C1]], [[SHL]]
|
|
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
|
|
; UNPACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; UNPACKED: $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
; PACKED-LABEL: name: image_load_v4f16_dmask_1000
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; PACKED: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)
|
|
; PACKED: $vgpr1 = COPY [[DEF]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
%tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
|
ret <4 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps <4 x half> @image_load_v4f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_v4f16_dmask_0000
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
|
|
; UNPACKED: $vgpr0 = COPY [[UV]](<2 x s16>)
|
|
; UNPACKED: $vgpr1 = COPY [[UV1]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
; PACKED-LABEL: name: image_load_v4f16_dmask_0000
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
|
|
; PACKED: $vgpr0 = COPY [[UV]](<2 x s16>)
|
|
; PACKED: $vgpr1 = COPY [[UV1]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
%tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
|
ret <4 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps half @image_load_tfe_f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_tfe_f16_dmask_0000
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; UNPACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; UNPACKED: $vgpr0 = COPY [[COPY10]](s32)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
|
|
; PACKED-LABEL: name: image_load_tfe_f16_dmask_0000
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; PACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; PACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; PACKED: $vgpr0 = COPY [[COPY10]](s32)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
|
|
%res = call { half, i32 } @llvm.amdgcn.image.load.2d.sl_f16i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
|
%tex = extractvalue { half, i32 } %res, 0
|
|
%tfe = extractvalue { half, i32 } %res, 1
|
|
store i32 %tfe, i32 addrspace(1)* undef
|
|
ret half %tex
|
|
}
|
|
|
|
define amdgpu_ps <2 x half> @image_load_tfe_v2f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_tfe_v2f16_dmask_1000
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; UNPACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
|
|
; PACKED-LABEL: name: image_load_tfe_v2f16_dmask_1000
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; PACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
|
|
; PACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; PACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
|
|
%res = call { <2 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v2f16i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
|
%tex = extractvalue { <2 x half>, i32 } %res, 0
|
|
%tfe = extractvalue { <2 x half>, i32 } %res, 1
|
|
store i32 %tfe, i32 addrspace(1)* undef
|
|
ret <2 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps <2 x half> @image_load_tfe_v2f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_tfe_v2f16_dmask_0000
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; UNPACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
|
|
; PACKED-LABEL: name: image_load_tfe_v2f16_dmask_0000
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; PACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
|
|
; PACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; PACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
|
|
%res = call { <2 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v2f16i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
|
%tex = extractvalue { <2 x half>, i32 } %res, 0
|
|
%tfe = extractvalue { <2 x half>, i32 } %res, 1
|
|
store i32 %tfe, i32 addrspace(1)* undef
|
|
ret <2 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps <3 x half> @image_load_tfe_v3f16_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_tfe_v3f16_dmask_1100
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
|
|
; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
|
|
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]
|
|
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
|
|
; UNPACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
|
|
; UNPACKED: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
|
|
; UNPACKED: G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; UNPACKED: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0
|
|
; UNPACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
|
|
; UNPACKED: [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
|
|
; UNPACKED: $vgpr0 = COPY [[EXTRACT1]](<2 x s16>)
|
|
; UNPACKED: $vgpr1 = COPY [[EXTRACT2]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
; PACKED-LABEL: name: image_load_tfe_v3f16_dmask_1100
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
|
|
; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; PACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
|
|
; PACKED: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[DEF1]](<2 x s16>), [[DEF1]](<2 x s16>)
|
|
; PACKED: [[UV2:%[0-9]+]]:_(<3 x s16>), [[UV3:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
|
|
; PACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; PACKED: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[UV2]](<3 x s16>), 0
|
|
; PACKED: [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
|
|
; PACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
|
|
; PACKED: $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
|
|
; PACKED: $vgpr1 = COPY [[EXTRACT1]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
%res = call { <3 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f16i32s.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
|
%tex = extractvalue { <3 x half>, i32 } %res, 0
|
|
%tfe = extractvalue { <3 x half>, i32 } %res, 1
|
|
store i32 %tfe, i32 addrspace(1)* undef
|
|
ret <3 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps <3 x half> @image_load_tfe_v3f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_tfe_v3f16_dmask_1000
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C1]], [[SHL]]
|
|
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
|
|
; UNPACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
|
|
; UNPACKED: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
|
|
; UNPACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; UNPACKED: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0
|
|
; UNPACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
|
|
; UNPACKED: [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
|
|
; UNPACKED: $vgpr0 = COPY [[EXTRACT1]](<2 x s16>)
|
|
; UNPACKED: $vgpr1 = COPY [[EXTRACT2]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
; PACKED-LABEL: name: image_load_tfe_v3f16_dmask_1000
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; PACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
|
|
; PACKED: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[DEF1]](<2 x s16>), [[DEF1]](<2 x s16>)
|
|
; PACKED: [[UV2:%[0-9]+]]:_(<3 x s16>), [[UV3:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
|
|
; PACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; PACKED: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[UV2]](<3 x s16>), 0
|
|
; PACKED: [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
|
|
; PACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
|
|
; PACKED: $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
|
|
; PACKED: $vgpr1 = COPY [[EXTRACT1]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
%res = call { <3 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f16i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
|
%tex = extractvalue { <3 x half>, i32 } %res, 0
|
|
%tfe = extractvalue { <3 x half>, i32 } %res, 1
|
|
store i32 %tfe, i32 addrspace(1)* undef
|
|
ret <3 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps <3 x half> @image_load_tfe_v3f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_tfe_v3f16_dmask_0000
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C1]], [[SHL]]
|
|
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
|
|
; UNPACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
|
|
; UNPACKED: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
|
|
; UNPACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; UNPACKED: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0
|
|
; UNPACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
|
|
; UNPACKED: [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
|
|
; UNPACKED: $vgpr0 = COPY [[EXTRACT1]](<2 x s16>)
|
|
; UNPACKED: $vgpr1 = COPY [[EXTRACT2]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
; PACKED-LABEL: name: image_load_tfe_v3f16_dmask_0000
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; PACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
|
|
; PACKED: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[DEF1]](<2 x s16>), [[DEF1]](<2 x s16>)
|
|
; PACKED: [[UV2:%[0-9]+]]:_(<3 x s16>), [[UV3:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
|
|
; PACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; PACKED: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[UV2]](<3 x s16>), 0
|
|
; PACKED: [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
|
|
; PACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
|
|
; PACKED: $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
|
|
; PACKED: $vgpr1 = COPY [[EXTRACT1]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
%res = call { <3 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f16i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
|
%tex = extractvalue { <3 x half>, i32 } %res, 0
|
|
%tfe = extractvalue { <3 x half>, i32 } %res, 1
|
|
store i32 %tfe, i32 addrspace(1)* undef
|
|
ret <3 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_1110(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_tfe_v4f16_dmask_1110
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
|
|
; UNPACKED: G_STORE [[UV3]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
|
|
; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
|
|
; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
|
|
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
|
|
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
|
|
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
|
|
; UNPACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; UNPACKED: $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
; PACKED-LABEL: name: image_load_tfe_v4f16_dmask_1110
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
|
|
; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
|
|
; PACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
|
|
; PACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV1]](s32)
|
|
; PACKED: G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; PACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; PACKED: $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
%res = call { <4 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f16i32s.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
|
%tex = extractvalue { <4 x half>, i32 } %res, 0
|
|
%tfe = extractvalue { <4 x half>, i32 } %res, 1
|
|
store i32 %tfe, i32 addrspace(1)* undef
|
|
ret <4 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_tfe_v4f16_dmask_1100
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
|
|
; UNPACKED: G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
|
|
; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
|
|
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]
|
|
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
|
|
; UNPACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; UNPACKED: $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
; PACKED-LABEL: name: image_load_tfe_v4f16_dmask_1100
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
|
|
; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; PACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
|
|
; PACKED: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; PACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; PACKED: $vgpr1 = COPY [[DEF1]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
%res = call { <4 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f16i32s.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
|
%tex = extractvalue { <4 x half>, i32 } %res, 0
|
|
%tfe = extractvalue { <4 x half>, i32 } %res, 1
|
|
store i32 %tfe, i32 addrspace(1)* undef
|
|
ret <4 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_tfe_v4f16_dmask_1000
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; UNPACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C1]], [[SHL]]
|
|
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
|
|
; UNPACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; UNPACKED: $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
; PACKED-LABEL: name: image_load_tfe_v4f16_dmask_1000
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; PACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
|
|
; PACKED: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; PACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; PACKED: $vgpr1 = COPY [[DEF1]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
%res = call { <4 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f16i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
|
%tex = extractvalue { <4 x half>, i32 } %res, 0
|
|
%tfe = extractvalue { <4 x half>, i32 } %res, 1
|
|
store i32 %tfe, i32 addrspace(1)* undef
|
|
ret <4 x half> %tex
|
|
}
|
|
|
|
define amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
|
; UNPACKED-LABEL: name: image_load_tfe_v4f16_dmask_0000
|
|
; UNPACKED: bb.1 (%ir-block.0):
|
|
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; UNPACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
|
|
; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
|
|
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
|
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
|
|
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
|
|
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
|
|
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C1]], [[SHL]]
|
|
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
|
|
; UNPACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; UNPACKED: $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
|
|
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
; PACKED-LABEL: name: image_load_tfe_v4f16_dmask_0000
|
|
; PACKED: bb.1 (%ir-block.0):
|
|
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
|
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
|
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
|
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
|
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
|
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
|
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
|
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
|
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
|
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
|
; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
|
; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
|
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
|
|
; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
|
; PACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
|
|
; PACKED: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
|
|
; PACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
|
; PACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
|
|
; PACKED: $vgpr1 = COPY [[DEF1]](<2 x s16>)
|
|
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
|
%res = call { <4 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f16i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
|
%tex = extractvalue { <4 x half>, i32 } %res, 0
|
|
%tfe = extractvalue { <4 x half>, i32 } %res, 1
|
|
store i32 %tfe, i32 addrspace(1)* undef
|
|
ret <4 x half> %tex
|
|
}
|
|
|
|
declare half @llvm.amdgcn.image.load.2d.f16.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
|
|
declare <2 x half> @llvm.amdgcn.image.load.2d.v2f16.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
|
|
declare <3 x half> @llvm.amdgcn.image.load.2d.v3f16.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
|
|
declare <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
|
|
declare { half, i32 } @llvm.amdgcn.image.load.2d.sl_f16i32s.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
|
|
declare { <2 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v2f16i32s.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
|
|
declare { <3 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f16i32s.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
|
|
declare { <4 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f16i32s.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
|
|
|
|
attributes #0 = { nounwind readonly }
|