forked from OSchip/llvm-project
56 lines
1.9 KiB
YAML
56 lines
1.9 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
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---
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name: constant
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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; GCN-LABEL: name: constant
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%0:vgpr(p1) = COPY $vgpr0_vgpr1
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%1:vgpr(p1) = COPY $vgpr2_vgpr3
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; GCN: %{{[0-9]+}}:sreg_32 = S_MOV_B32 1
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%2:sreg_32(s32) = G_CONSTANT i32 1
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; GCN: [[LO0:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: [[HI0:%[0-9]+]]:sreg_32 = S_MOV_B32 1
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; GCN: %{{[0-9]+}}:sreg_64 = REG_SEQUENCE [[LO0]], %subreg.sub0, [[HI0]], %subreg.sub1
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%3:sgpr(s64) = G_CONSTANT i64 4294967296
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; GCN: %{{[0-9]+}}:sreg_32 = S_MOV_B32 1065353216
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%4:sgpr(s32) = G_FCONSTANT float 1.0
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; GCN: %5:sreg_64 = S_MOV_B64 4607182418800017408
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%5:sgpr(s64) = G_FCONSTANT double 1.0
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; GCN: [[LO1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: [[HI1:%[0-9]+]]:sreg_32 = S_MOV_B32 1076101120
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; GCN: %{{[0-9]+}}:sreg_64 = REG_SEQUENCE [[LO1]], %subreg.sub0, [[HI1]], %subreg.sub1
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%6:sgpr(s64) = G_FCONSTANT double 10.0
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; GCN: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 1
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%7:vgpr(s32) = G_CONSTANT i32 1
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; GCN: [[LO2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0
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; GCN: [[HI2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1
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; GCN: %{{[0-9]+}}:vreg_64 = REG_SEQUENCE [[LO2]], %subreg.sub0, [[HI2]], %subreg.sub1
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%8:vgpr(s64) = G_CONSTANT i64 4294967296
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; GCN: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 1065353216
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%9:vgpr(s32) = G_FCONSTANT float 1.0
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; GCN: [[LO3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0
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; GCN: [[HI3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1072693248
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; GCN: %{{[0-9]+}}:vreg_64 = REG_SEQUENCE [[LO3]], %subreg.sub0, [[HI3]], %subreg.sub1
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%10:vgpr(s64) = G_FCONSTANT double 1.0
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S_ENDPGM 0, implicit %2, implicit %4, implicit %5, implicit %6, implicit %8, implicit %3, implicit %5, implicit %7, implicit %9, implicit %10
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...
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