forked from OSchip/llvm-project
737 lines
26 KiB
C++
737 lines
26 KiB
C++
//===----- HexagonMCChecker.cpp - Instruction bundle checking -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the checking of insns inside a bundle according to the
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// packet constraint rules of the Hexagon ISA.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/HexagonMCChecker.h"
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#include "Hexagon.h"
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "MCTargetDesc/HexagonMCShuffler.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/SourceMgr.h"
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#include <cassert>
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using namespace llvm;
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static cl::opt<bool>
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RelaxNVChecks("relax-nv-checks", cl::init(false), cl::ZeroOrMore,
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cl::Hidden, cl::desc("Relax checks of new-value validity"));
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const HexagonMCChecker::PredSense
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HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);
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void HexagonMCChecker::init() {
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// Initialize read-only registers set.
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ReadOnly.insert(Hexagon::PC);
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ReadOnly.insert(Hexagon::C9_8);
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// Figure out the loop-registers definitions.
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if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
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Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0?
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Defs[Hexagon::LC0].insert(Unconditional);
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}
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if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
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Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0?
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Defs[Hexagon::LC1].insert(Unconditional);
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}
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if (HexagonMCInstrInfo::isBundle(MCB))
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// Unfurl a bundle.
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for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
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MCInst const &Inst = *I.getInst();
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if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
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init(*Inst.getOperand(0).getInst());
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init(*Inst.getOperand(1).getInst());
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} else
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init(Inst);
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}
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else
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init(MCB);
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}
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void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg,
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bool &isTrue) {
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if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) {
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// Note an used predicate register.
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PredReg = R;
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isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI);
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// Note use of new predicate register.
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if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
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NewPreds.insert(PredReg);
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} else
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// Note register use. Super-registers are not tracked directly,
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// but their components.
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for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
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SRI.isValid(); ++SRI)
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if (!MCSubRegIterator(*SRI, &RI).isValid())
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// Skip super-registers used indirectly.
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Uses.insert(*SRI);
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}
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void HexagonMCChecker::init(MCInst const &MCI) {
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const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI);
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unsigned PredReg = Hexagon::NoRegister;
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bool isTrue = false;
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// Get used registers.
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for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
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if (MCI.getOperand(i).isReg())
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initReg(MCI, MCI.getOperand(i).getReg(), PredReg, isTrue);
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for (unsigned i = 0; i < MCID.getNumImplicitUses(); ++i)
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initReg(MCI, MCID.getImplicitUses()[i], PredReg, isTrue);
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// Get implicit register definitions.
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if (const MCPhysReg *ImpDef = MCID.getImplicitDefs())
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for (; *ImpDef; ++ImpDef) {
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unsigned R = *ImpDef;
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if (Hexagon::R31 != R && MCID.isCall())
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// Any register other than the LR and the PC are actually volatile ones
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// as defined by the ABI, not modified implicitly by the call insn.
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continue;
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if (Hexagon::PC == R)
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// Branches are the only insns that can change the PC,
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// otherwise a read-only register.
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continue;
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if (Hexagon::USR_OVF == R)
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// Many insns change the USR implicitly, but only one or another flag.
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// The instruction table models the USR.OVF flag, which can be
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// implicitly modified more than once, but cannot be modified in the
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// same packet with an instruction that modifies is explicitly. Deal
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// with such situations individually.
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SoftDefs.insert(R);
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else if (isPredicateRegister(R) &&
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HexagonMCInstrInfo::isPredicateLate(MCII, MCI))
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// Include implicit late predicates.
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LatePreds.insert(R);
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else
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Defs[R].insert(PredSense(PredReg, isTrue));
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}
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// Figure out explicit register definitions.
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for (unsigned i = 0; i < MCID.getNumDefs(); ++i) {
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unsigned R = MCI.getOperand(i).getReg(), S = Hexagon::NoRegister;
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// USR has subregisters (while C8 does not for technical reasons), so
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// reset R to USR, since we know how to handle multiple defs of USR,
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// taking into account its subregisters.
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if (R == Hexagon::C8)
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R = Hexagon::USR;
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// Note register definitions, direct ones as well as indirect side-effects.
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// Super-registers are not tracked directly, but their components.
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for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
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SRI.isValid(); ++SRI) {
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if (MCSubRegIterator(*SRI, &RI).isValid())
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// Skip super-registers defined indirectly.
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continue;
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if (R == *SRI) {
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if (S == R)
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// Avoid scoring the defined register multiple times.
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continue;
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else
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// Note that the defined register has already been scored.
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S = R;
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}
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if (Hexagon::P3_0 != R && Hexagon::P3_0 == *SRI)
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// P3:0 is a special case, since multiple predicate register definitions
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// in a packet is allowed as the equivalent of their logical "and".
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// Only an explicit definition of P3:0 is noted as such; if a
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// side-effect, then note as a soft definition.
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SoftDefs.insert(*SRI);
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else if (HexagonMCInstrInfo::isPredicateLate(MCII, MCI) &&
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isPredicateRegister(*SRI))
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// Some insns produce predicates too late to be used in the same packet.
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LatePreds.insert(*SRI);
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else if (i == 0 && HexagonMCInstrInfo::getType(MCII, MCI) ==
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HexagonII::TypeCVI_VM_TMP_LD)
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// Temporary loads should be used in the same packet, but don't commit
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// results, so it should be disregarded if another insn changes the same
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// register.
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// TODO: relies on the impossibility of a current and a temporary loads
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// in the same packet.
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TmpDefs.insert(*SRI);
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else if (i <= 1 && HexagonMCInstrInfo::hasNewValue2(MCII, MCI))
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// vshuff(Vx, Vy, Rx) <- Vx(0) and Vy(1) are both source and
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// destination registers with this instruction. same for vdeal(Vx,Vy,Rx)
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Uses.insert(*SRI);
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else
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Defs[*SRI].insert(PredSense(PredReg, isTrue));
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}
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}
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// Figure out definitions of new predicate registers.
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if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
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for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
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if (MCI.getOperand(i).isReg()) {
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unsigned P = MCI.getOperand(i).getReg();
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if (isPredicateRegister(P))
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NewPreds.insert(P);
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}
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}
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HexagonMCChecker::HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII,
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MCSubtargetInfo const &STI, MCInst &mcb,
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MCRegisterInfo const &ri, bool ReportErrors)
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: Context(Context), MCB(mcb), RI(ri), MCII(MCII), STI(STI),
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ReportErrors(ReportErrors) {
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init();
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}
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HexagonMCChecker::HexagonMCChecker(HexagonMCChecker const &Other,
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MCSubtargetInfo const &STI,
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bool CopyReportErrors)
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: Context(Other.Context), MCB(Other.MCB), RI(Other.RI), MCII(Other.MCII),
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STI(STI), ReportErrors(CopyReportErrors ? Other.ReportErrors : false) {}
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bool HexagonMCChecker::check(bool FullCheck) {
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bool chkP = checkPredicates();
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bool chkNV = checkNewValues();
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bool chkR = checkRegisters();
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bool chkRRO = checkRegistersReadOnly();
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checkRegisterCurDefs();
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bool chkS = checkSolo();
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bool chkSh = true;
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if (FullCheck)
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chkSh = checkShuffle();
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bool chkSl = true;
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if (FullCheck)
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chkSl = checkSlots();
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bool chkAXOK = checkAXOK();
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bool chkCofMax1 = checkCOFMax1();
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bool chkHWLoop = checkHWLoop();
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bool chk = chkP && chkNV && chkR && chkRRO && chkS && chkSh && chkSl &&
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chkAXOK && chkCofMax1 && chkHWLoop;
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return chk;
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}
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static bool isDuplexAGroup(unsigned Opcode) {
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switch (Opcode) {
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case Hexagon::SA1_addi:
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case Hexagon::SA1_addrx:
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case Hexagon::SA1_addsp:
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case Hexagon::SA1_and1:
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case Hexagon::SA1_clrf:
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case Hexagon::SA1_clrfnew:
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case Hexagon::SA1_clrt:
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case Hexagon::SA1_clrtnew:
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case Hexagon::SA1_cmpeqi:
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case Hexagon::SA1_combine0i:
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case Hexagon::SA1_combine1i:
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case Hexagon::SA1_combine2i:
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case Hexagon::SA1_combine3i:
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case Hexagon::SA1_combinerz:
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case Hexagon::SA1_combinezr:
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case Hexagon::SA1_dec:
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case Hexagon::SA1_inc:
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case Hexagon::SA1_seti:
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case Hexagon::SA1_setin1:
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case Hexagon::SA1_sxtb:
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case Hexagon::SA1_sxth:
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case Hexagon::SA1_tfr:
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case Hexagon::SA1_zxtb:
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case Hexagon::SA1_zxth:
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return true;
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break;
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default:
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return false;
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}
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}
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static bool isNeitherAnorX(MCInstrInfo const &MCII, MCInst const &ID) {
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unsigned Result = 0;
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unsigned Type = HexagonMCInstrInfo::getType(MCII, ID);
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if (Type == HexagonII::TypeDUPLEX) {
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unsigned subInst0Opcode = ID.getOperand(0).getInst()->getOpcode();
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unsigned subInst1Opcode = ID.getOperand(1).getInst()->getOpcode();
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Result += !isDuplexAGroup(subInst0Opcode);
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Result += !isDuplexAGroup(subInst1Opcode);
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} else
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Result +=
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Type != HexagonII::TypeALU32_2op && Type != HexagonII::TypeALU32_3op &&
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Type != HexagonII::TypeALU32_ADDI && Type != HexagonII::TypeS_2op &&
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Type != HexagonII::TypeS_3op &&
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(Type != HexagonII::TypeALU64 || HexagonMCInstrInfo::isFloat(MCII, ID));
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return Result != 0;
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}
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bool HexagonMCChecker::checkAXOK() {
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MCInst const *HasSoloAXInst = nullptr;
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for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
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if (HexagonMCInstrInfo::isSoloAX(MCII, I)) {
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HasSoloAXInst = &I;
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}
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}
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if (!HasSoloAXInst)
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return true;
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for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
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if (&I != HasSoloAXInst && isNeitherAnorX(MCII, I)) {
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reportError(
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HasSoloAXInst->getLoc(),
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Twine("Instruction can only be in a packet with ALU or non-FPU XTYPE "
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"instructions"));
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reportError(I.getLoc(),
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Twine("Not an ALU or non-FPU XTYPE instruction"));
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return false;
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}
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}
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return true;
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}
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void HexagonMCChecker::reportBranchErrors() {
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for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
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MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
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if (Desc.isBranch() || Desc.isCall() || Desc.isReturn())
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reportNote(I.getLoc(), "Branching instruction");
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}
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}
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bool HexagonMCChecker::checkHWLoop() {
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if (!HexagonMCInstrInfo::isInnerLoop(MCB) &&
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!HexagonMCInstrInfo::isOuterLoop(MCB))
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return true;
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for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
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MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
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if (Desc.isBranch() || Desc.isCall() || Desc.isReturn()) {
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reportError(MCB.getLoc(),
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"Branches cannot be in a packet with hardware loops");
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reportBranchErrors();
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return false;
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}
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}
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return true;
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}
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bool HexagonMCChecker::checkCOFMax1() {
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SmallVector<MCInst const *, 2> BranchLocations;
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for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
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MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
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if (Desc.isBranch() || Desc.isCall() || Desc.isReturn())
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BranchLocations.push_back(&I);
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}
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for (unsigned J = 0, N = BranchLocations.size(); J < N; ++J) {
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MCInst const &I = *BranchLocations[J];
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if (HexagonMCInstrInfo::isCofMax1(MCII, I)) {
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bool Relax1 = HexagonMCInstrInfo::isCofRelax1(MCII, I);
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bool Relax2 = HexagonMCInstrInfo::isCofRelax2(MCII, I);
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if (N > 1 && !Relax1 && !Relax2) {
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reportError(I.getLoc(),
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"Instruction may not be in a packet with other branches");
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reportBranchErrors();
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return false;
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}
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if (N > 1 && J == 0 && !Relax1) {
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reportError(I.getLoc(),
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"Instruction may not be the first branch in packet");
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reportBranchErrors();
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return false;
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}
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if (N > 1 && J == 1 && !Relax2) {
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reportError(I.getLoc(),
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"Instruction may not be the second branch in packet");
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reportBranchErrors();
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return false;
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}
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}
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}
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return true;
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}
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bool HexagonMCChecker::checkSlots() {
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unsigned slotsUsed = 0;
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for (auto HMI : HexagonMCInstrInfo::bundleInstructions(MCB)) {
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MCInst const &MCI = *HMI.getInst();
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if (HexagonMCInstrInfo::isImmext(MCI))
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continue;
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if (HexagonMCInstrInfo::isDuplex(MCII, MCI))
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slotsUsed += 2;
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else
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++slotsUsed;
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}
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if (slotsUsed > HEXAGON_PACKET_SIZE) {
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reportError("invalid instruction packet: out of slots");
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return false;
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}
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return true;
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}
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// Check legal use of predicate registers.
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bool HexagonMCChecker::checkPredicates() {
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// Check for proper use of new predicate registers.
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for (const auto &I : NewPreds) {
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unsigned P = I;
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if (!Defs.count(P) || LatePreds.count(P)) {
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// Error out if the new predicate register is not defined,
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// or defined "late"
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// (e.g., "{ if (p3.new)... ; p3 = sp1loop0(#r7:2, Rs) }").
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reportErrorNewValue(P);
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return false;
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}
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}
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// Check for proper use of auto-anded of predicate registers.
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for (const auto &I : LatePreds) {
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unsigned P = I;
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if (LatePreds.count(P) > 1 || Defs.count(P)) {
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// Error out if predicate register defined "late" multiple times or
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// defined late and regularly defined
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// (e.g., "{ p3 = sp1loop0(...); p3 = cmp.eq(...) }".
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reportErrorRegisters(P);
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return false;
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}
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}
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return true;
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}
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// Check legal use of new values.
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bool HexagonMCChecker::checkNewValues() {
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for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
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if (!HexagonMCInstrInfo::isNewValue(MCII, I))
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continue;
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auto Consumer = HexagonMCInstrInfo::predicateInfo(MCII, I);
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bool Branch = HexagonMCInstrInfo::getDesc(MCII, I).isBranch();
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MCOperand const &Op = HexagonMCInstrInfo::getNewValueOperand(MCII, I);
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assert(Op.isReg());
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auto Producer = registerProducer(Op.getReg(), Consumer);
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if (std::get<0>(Producer) == nullptr) {
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reportError(I.getLoc(), "New value register consumer has no producer");
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return false;
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}
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if (!RelaxNVChecks) {
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// Checks that statically prove correct new value consumption
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if (std::get<2>(Producer).isPredicated() &&
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(!Consumer.isPredicated() ||
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llvm::HexagonMCInstrInfo::getType(MCII, I) == HexagonII::TypeNCJ)) {
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reportNote(
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std::get<0>(Producer)->getLoc(),
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"Register producer is predicated and consumer is unconditional");
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reportError(I.getLoc(),
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"Instruction does not have a valid new register producer");
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return false;
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}
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if (std::get<2>(Producer).Register != Hexagon::NoRegister &&
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std::get<2>(Producer).Register != Consumer.Register) {
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reportNote(std::get<0>(Producer)->getLoc(),
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"Register producer does not use the same predicate "
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"register as the consumer");
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reportError(I.getLoc(),
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"Instruction does not have a valid new register producer");
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return false;
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}
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}
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if (std::get<2>(Producer).Register == Consumer.Register &&
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Consumer.PredicatedTrue != std::get<2>(Producer).PredicatedTrue) {
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reportNote(
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std::get<0>(Producer)->getLoc(),
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"Register producer has the opposite predicate sense as consumer");
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reportError(I.getLoc(),
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"Instruction does not have a valid new register producer");
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return false;
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}
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MCInstrDesc const &Desc =
|
|
HexagonMCInstrInfo::getDesc(MCII, *std::get<0>(Producer));
|
|
if (Desc.OpInfo[std::get<1>(Producer)].RegClass ==
|
|
Hexagon::DoubleRegsRegClassID) {
|
|
reportNote(std::get<0>(Producer)->getLoc(),
|
|
"Double registers cannot be new-value producers");
|
|
reportError(I.getLoc(),
|
|
"Instruction does not have a valid new register producer");
|
|
return false;
|
|
}
|
|
if ((Desc.mayLoad() && std::get<1>(Producer) == 1) ||
|
|
(Desc.mayStore() && std::get<1>(Producer) == 0)) {
|
|
unsigned Mode =
|
|
HexagonMCInstrInfo::getAddrMode(MCII, *std::get<0>(Producer));
|
|
StringRef ModeError;
|
|
if (Mode == HexagonII::AbsoluteSet)
|
|
ModeError = "Absolute-set";
|
|
if (Mode == HexagonII::PostInc)
|
|
ModeError = "Auto-increment";
|
|
if (!ModeError.empty()) {
|
|
reportNote(std::get<0>(Producer)->getLoc(),
|
|
ModeError + " registers cannot be a new-value "
|
|
"producer");
|
|
reportError(I.getLoc(),
|
|
"Instruction does not have a valid new register producer");
|
|
return false;
|
|
}
|
|
}
|
|
if (Branch && HexagonMCInstrInfo::isFloat(MCII, *std::get<0>(Producer))) {
|
|
reportNote(std::get<0>(Producer)->getLoc(),
|
|
"FPU instructions cannot be new-value producers for jumps");
|
|
reportError(I.getLoc(),
|
|
"Instruction does not have a valid new register producer");
|
|
return false;
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool HexagonMCChecker::checkRegistersReadOnly() {
|
|
for (auto I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
|
|
MCInst const &Inst = *I.getInst();
|
|
unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs();
|
|
for (unsigned j = 0; j < Defs; ++j) {
|
|
MCOperand const &Operand = Inst.getOperand(j);
|
|
assert(Operand.isReg() && "Def is not a register");
|
|
unsigned Register = Operand.getReg();
|
|
if (ReadOnly.find(Register) != ReadOnly.end()) {
|
|
reportError(Inst.getLoc(), "Cannot write to read-only register `" +
|
|
Twine(RI.getName(Register)) + "'");
|
|
return false;
|
|
}
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool HexagonMCChecker::registerUsed(unsigned Register) {
|
|
for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB))
|
|
for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(),
|
|
n = I.getNumOperands();
|
|
j < n; ++j) {
|
|
MCOperand const &Operand = I.getOperand(j);
|
|
if (Operand.isReg() && Operand.getReg() == Register)
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
|
|
HexagonMCChecker::registerProducer(
|
|
unsigned Register, HexagonMCInstrInfo::PredicateInfo ConsumerPredicate) {
|
|
std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
|
|
WrongSense;
|
|
for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
|
|
MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
|
|
auto ProducerPredicate = HexagonMCInstrInfo::predicateInfo(MCII, I);
|
|
for (unsigned J = 0, N = Desc.getNumDefs(); J < N; ++J)
|
|
for (auto K = MCRegAliasIterator(I.getOperand(J).getReg(), &RI, true);
|
|
K.isValid(); ++K)
|
|
if (*K == Register) {
|
|
if (RelaxNVChecks ||
|
|
(ProducerPredicate.Register == ConsumerPredicate.Register &&
|
|
(ProducerPredicate.Register == Hexagon::NoRegister ||
|
|
ProducerPredicate.PredicatedTrue ==
|
|
ConsumerPredicate.PredicatedTrue)))
|
|
return std::make_tuple(&I, J, ProducerPredicate);
|
|
std::get<0>(WrongSense) = &I;
|
|
std::get<1>(WrongSense) = J;
|
|
std::get<2>(WrongSense) = ProducerPredicate;
|
|
}
|
|
if (Register == Hexagon::VTMP && HexagonMCInstrInfo::hasTmpDst(MCII, I))
|
|
return std::make_tuple(&I, 0, HexagonMCInstrInfo::PredicateInfo());
|
|
}
|
|
return WrongSense;
|
|
}
|
|
|
|
void HexagonMCChecker::checkRegisterCurDefs() {
|
|
for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
|
|
if (HexagonMCInstrInfo::isCVINew(MCII, I) &&
|
|
HexagonMCInstrInfo::getDesc(MCII, I).mayLoad()) {
|
|
unsigned Register = I.getOperand(0).getReg();
|
|
if (!registerUsed(Register))
|
|
reportWarning("Register `" + Twine(RI.getName(Register)) +
|
|
"' used with `.cur' "
|
|
"but not used in the same packet");
|
|
}
|
|
}
|
|
}
|
|
|
|
// Check for legal register uses and definitions.
|
|
bool HexagonMCChecker::checkRegisters() {
|
|
// Check for proper register definitions.
|
|
for (const auto &I : Defs) {
|
|
unsigned R = I.first;
|
|
|
|
if (isLoopRegister(R) && Defs.count(R) > 1 &&
|
|
(HexagonMCInstrInfo::isInnerLoop(MCB) ||
|
|
HexagonMCInstrInfo::isOuterLoop(MCB))) {
|
|
// Error out for definitions of loop registers at the end of a loop.
|
|
reportError("loop-setup and some branch instructions "
|
|
"cannot be in the same packet");
|
|
return false;
|
|
}
|
|
if (SoftDefs.count(R)) {
|
|
// Error out for explicit changes to registers also weakly defined
|
|
// (e.g., "{ usr = r0; r0 = sfadd(...) }").
|
|
unsigned UsrR = Hexagon::USR; // Silence warning about mixed types in ?:.
|
|
unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;
|
|
reportErrorRegisters(BadR);
|
|
return false;
|
|
}
|
|
if (!isPredicateRegister(R) && Defs[R].size() > 1) {
|
|
// Check for multiple register definitions.
|
|
PredSet &PM = Defs[R];
|
|
|
|
// Check for multiple unconditional register definitions.
|
|
if (PM.count(Unconditional)) {
|
|
// Error out on an unconditional change when there are any other
|
|
// changes, conditional or not.
|
|
unsigned UsrR = Hexagon::USR;
|
|
unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;
|
|
reportErrorRegisters(BadR);
|
|
return false;
|
|
}
|
|
// Check for multiple conditional register definitions.
|
|
for (const auto &J : PM) {
|
|
PredSense P = J;
|
|
|
|
// Check for multiple uses of the same condition.
|
|
if (PM.count(P) > 1) {
|
|
// Error out on conditional changes based on the same predicate
|
|
// (e.g., "{ if (!p0) r0 =...; if (!p0) r0 =... }").
|
|
reportErrorRegisters(R);
|
|
return false;
|
|
}
|
|
// Check for the use of the complementary condition.
|
|
P.second = !P.second;
|
|
if (PM.count(P) && PM.size() > 2) {
|
|
// Error out on conditional changes based on the same predicate
|
|
// multiple times
|
|
// (e.g., "if (p0) r0 =...; if (!p0) r0 =... }; if (!p0) r0 =...").
|
|
reportErrorRegisters(R);
|
|
return false;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Check for use of temporary definitions.
|
|
for (const auto &I : TmpDefs) {
|
|
unsigned R = I;
|
|
|
|
if (!Uses.count(R)) {
|
|
// special case for vhist
|
|
bool vHistFound = false;
|
|
for (auto const &HMI : HexagonMCInstrInfo::bundleInstructions(MCB)) {
|
|
if (HexagonMCInstrInfo::getType(MCII, *HMI.getInst()) ==
|
|
HexagonII::TypeCVI_HIST) {
|
|
vHistFound = true; // vhist() implicitly uses ALL REGxx.tmp
|
|
break;
|
|
}
|
|
}
|
|
// Warn on an unused temporary definition.
|
|
if (!vHistFound) {
|
|
reportWarning("register `" + Twine(RI.getName(R)) +
|
|
"' used with `.tmp' but not used in the same packet");
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
// Check for legal use of solo insns.
|
|
bool HexagonMCChecker::checkSolo() {
|
|
if (HexagonMCInstrInfo::bundleSize(MCB) > 1)
|
|
for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
|
|
if (HexagonMCInstrInfo::isSolo(MCII, I)) {
|
|
reportError(I.getLoc(), "Instruction is marked `isSolo' and "
|
|
"cannot have other instructions in "
|
|
"the same packet");
|
|
return false;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool HexagonMCChecker::checkShuffle() {
|
|
HexagonMCShuffler MCSDX(Context, ReportErrors, MCII, STI, MCB);
|
|
return MCSDX.check();
|
|
}
|
|
|
|
void HexagonMCChecker::compoundRegisterMap(unsigned &Register) {
|
|
switch (Register) {
|
|
default:
|
|
break;
|
|
case Hexagon::R15:
|
|
Register = Hexagon::R23;
|
|
break;
|
|
case Hexagon::R14:
|
|
Register = Hexagon::R22;
|
|
break;
|
|
case Hexagon::R13:
|
|
Register = Hexagon::R21;
|
|
break;
|
|
case Hexagon::R12:
|
|
Register = Hexagon::R20;
|
|
break;
|
|
case Hexagon::R11:
|
|
Register = Hexagon::R19;
|
|
break;
|
|
case Hexagon::R10:
|
|
Register = Hexagon::R18;
|
|
break;
|
|
case Hexagon::R9:
|
|
Register = Hexagon::R17;
|
|
break;
|
|
case Hexagon::R8:
|
|
Register = Hexagon::R16;
|
|
break;
|
|
}
|
|
}
|
|
|
|
void HexagonMCChecker::reportErrorRegisters(unsigned Register) {
|
|
reportError("register `" + Twine(RI.getName(Register)) +
|
|
"' modified more than once");
|
|
}
|
|
|
|
void HexagonMCChecker::reportErrorNewValue(unsigned Register) {
|
|
reportError("register `" + Twine(RI.getName(Register)) +
|
|
"' used with `.new' "
|
|
"but not validly modified in the same packet");
|
|
}
|
|
|
|
void HexagonMCChecker::reportError(Twine const &Msg) {
|
|
reportError(MCB.getLoc(), Msg);
|
|
}
|
|
|
|
void HexagonMCChecker::reportError(SMLoc Loc, Twine const &Msg) {
|
|
if (ReportErrors)
|
|
Context.reportError(Loc, Msg);
|
|
}
|
|
|
|
void HexagonMCChecker::reportNote(SMLoc Loc, llvm::Twine const &Msg) {
|
|
if (ReportErrors) {
|
|
auto SM = Context.getSourceManager();
|
|
if (SM)
|
|
SM->PrintMessage(Loc, SourceMgr::DK_Note, Msg);
|
|
}
|
|
}
|
|
|
|
void HexagonMCChecker::reportWarning(Twine const &Msg) {
|
|
if (ReportErrors) {
|
|
auto SM = Context.getSourceManager();
|
|
if (SM)
|
|
SM->PrintMessage(MCB.getLoc(), SourceMgr::DK_Warning, Msg);
|
|
}
|
|
}
|