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llvm-project/llvm/lib/Target/AArch64
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Aditya Nandakumar 500e3ead9f [GISel]: Add support for CSEing continuously during GISel passes. 
https://reviews.llvm.org/D52803

This patch adds support to continuously CSE instructions during
each of the GISel passes. It consists of a GISelCSEInfo analysis pass
that can be used by the CSEMIRBuilder.

llvm-svn: 351283
 		2019-01-16 00:40:37 +00:00
..
AsmParser [AArch64] Move feature predctrl to predres 2019-01-09 11:24:15 +00:00
Disassembler [AArch64][v8.5A] Add Memory Tagging instructions 2018-10-02 10:04:39 +00:00
InstPrinter [AArch64][v8.5A] Add Branch Target Identification instructions 2018-09-27 14:54:33 +00:00
MCTargetDesc [MC] [AArch64] Support resolving signed fixups for :abs_g0_s: etc. 2019-01-08 04:48:00 +00:00
TargetInfo
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Utils [AArch64] Emit the correct MCExpr relocations specifiers like VK_ABS_G0, etc 2019-01-10 04:59:44 +00:00
AArch64.h Introduce control flow speculation tracking pass for AArch64 2018-12-18 08:50:02 +00:00
AArch64.td [AArch64] Adjust the feature set for Exynos 2019-01-15 01:53:49 +00:00
AArch64A53Fix835769.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64A57FPLoadBalancing.cpp llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...) 2018-09-27 02:13:45 +00:00
AArch64AdvSIMDScalarPass.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64AsmPrinter.cpp [Dwarf/AArch64] Return address signing B key dwarf support 2018-12-21 10:45:08 +00:00
AArch64BranchTargets.cpp [AArch64][v8.5A] Branch Target Identification code-generation pass 2018-10-08 14:04:24 +00:00
AArch64CallLowering.cpp [AArch64] Support adding X[8-15,18] registers as CSRs. 2018-09-22 22:17:50 +00:00
AArch64CallLowering.h [GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per Value 2018-08-02 08:33:31 +00:00
AArch64CallingConvention.h
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AArch64CallingConvention.td AArch64: clean up some whitespace in Windows CC (NFC) 2018-12-04 22:19:29 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
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AArch64CollectLOH.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64CompressJumpTables.cpp AArch64: add a pass to compress jump-table entries when possible. 2018-10-24 20:19:09 +00:00
AArch64CondBrTuning.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64ConditionOptimizer.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64ConditionalCompares.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64DeadRegisterDefinitionsPass.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64ExpandPseudoInsts.cpp [AArch64] Add Tiny Code Model for AArch64 2018-08-22 11:31:39 +00:00
AArch64FalkorHWPFFix.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64FastISel.cpp Introduce control flow speculation tracking pass for AArch64 2018-12-18 08:50:02 +00:00
AArch64FrameLowering.cpp [Dwarf/AArch64] Return address signing B key dwarf support 2018-12-21 10:45:08 +00:00
AArch64FrameLowering.h [ARM64] [Windows] Handle funclets 2018-11-09 23:33:30 +00:00
AArch64GenRegisterBankInfo.def
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AArch64ISelDAGToDAG.cpp [AArch64] Always use the version of computeKnownBits that returns a value. NFCI. 2018-12-21 15:05:10 +00:00
AArch64ISelLowering.cpp [AArch64] Explicitly use v1i64 type for llvm.aarch64.neon.abs.i64 . 2019-01-15 00:15:24 +00:00
AArch64ISelLowering.h [ARM64] [Windows] Handle funclets 2018-11-09 23:33:30 +00:00
AArch64InstrAtomics.td
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AArch64InstrFormats.td [NFC][AArch64] Split out backend features 2018-12-06 15:39:17 +00:00
AArch64InstrInfo.cpp [AArch64] Emit the correct MCExpr relocations specifiers like VK_ABS_G0, etc 2019-01-10 04:59:44 +00:00
AArch64InstrInfo.h [AArch64] Refactor the Exynos scheduling predicates 2018-12-10 17:17:26 +00:00
AArch64InstrInfo.td Initial AArch64 SLH implementation. 2019-01-09 15:13:34 +00:00
AArch64InstructionSelector.cpp Fix build errors introduced by r349712 on aarch64 bots. 2018-12-20 03:27:42 +00:00
AArch64LegalizerInfo.cpp GlobalISel: Implement fewerElements for implicit_def 2019-01-09 07:51:52 +00:00
AArch64LegalizerInfo.h [GISel]: Provide standard interface to observe changes in GISel passes 2018-12-05 20:14:52 +00:00
AArch64LoadStoreOptimizer.cpp [MI] Change the array of `MachineMemOperand` pointers to be 2018-08-16 21:30:05 +00:00
AArch64MCInstLower.cpp [AArch64] Emit the correct MCExpr relocations specifiers like VK_ABS_G0, etc 2019-01-10 04:59:44 +00:00
AArch64MCInstLower.h
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AArch64MachineFunctionInfo.h [COFF, ARM64] Make sure to forward arguments from vararg to musttail vararg 2018-10-30 20:46:10 +00:00
AArch64MacroFusion.cpp [AArch64] Add new target feature to fuse arithmetic and logic operations 2019-01-14 23:54:36 +00:00
AArch64MacroFusion.h
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AArch64PBQPRegAlloc.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64PBQPRegAlloc.h
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AArch64PerfectShuffle.h
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AArch64PfmCounters.td [llvm-exegesis][NFC] Add a way to declare the default counter binding for unbound CPUs for a target. 2018-11-09 13:15:32 +00:00
AArch64PreLegalizerCombiner.cpp [GISel]: Add support for CSEing continuously during GISel passes. 2019-01-16 00:40:37 +00:00
AArch64PromoteConstant.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64RedundantCopyElimination.cpp [CodeGen][AArch64] Use RegUnits to track register aliases. (NFC) 2018-05-23 17:49:38 +00:00
AArch64RegisterBankInfo.cpp [GlobalISel][AArch64] Add G_FCEIL to isPreISelGenericFloatingPointOpcode 2018-12-20 21:14:15 +00:00
AArch64RegisterBankInfo.h
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AArch64RegisterBanks.td
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AArch64RegisterInfo.cpp Introduce control flow speculation tracking pass for AArch64 2018-12-18 08:50:02 +00:00
AArch64RegisterInfo.h [ARM64] [Windows] Handle funclets 2018-11-09 23:33:30 +00:00
AArch64RegisterInfo.td [AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI 2018-10-08 14:09:15 +00:00
AArch64SIMDInstrOpt.cpp [TargetSchedule] shrink interface for init(); NFCI 2018-04-08 19:56:04 +00:00
AArch64SVEInstrInfo.td [AArch64][SVE] Asm: Enable instructions to be prefixed. 2018-07-30 16:05:45 +00:00
AArch64SchedA53.td [AArch64] Clean-up a few over-eager regexps in models. 2018-03-23 11:00:42 +00:00
AArch64SchedA57.td
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AArch64SchedA57WriteRes.td
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AArch64SchedCyclone.td
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AArch64SchedExynosM1.td [AArch64] Adjust the cost model for Exynos 2019-01-08 22:29:58 +00:00
AArch64SchedExynosM3.td [AArch64] Adjust the cost model for Exynos 2019-01-08 22:29:58 +00:00
AArch64SchedExynosM4.td [AArch64] Add pipeline model for Exynos M4 2019-01-11 19:36:25 +00:00
AArch64SchedFalkor.td [TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. 2018-03-18 19:56:15 +00:00
AArch64SchedFalkorDetails.td [AArch64][Falkor] Correct load/store increment scheduling details 2018-03-20 13:46:35 +00:00
AArch64SchedKryo.td [TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. 2018-03-18 19:56:15 +00:00
AArch64SchedKryoDetails.td
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AArch64SchedPredExynos.td [AArch64] Improve Exynos predicates 2019-01-11 22:39:47 +00:00
AArch64SchedPredicates.td [AArch64] Add new scheduling predicates 2019-01-03 17:28:09 +00:00
AArch64SchedThunderX.td [TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. 2018-03-18 19:56:15 +00:00
AArch64SchedThunderX2T99.td [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles. 2018-06-13 09:41:49 +00:00
AArch64Schedule.td [AArch64] Refactor the scheduling predicates (3/3) (NFC) 2018-11-26 21:47:46 +00:00
AArch64SelectionDAGInfo.cpp
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AArch64SelectionDAGInfo.h
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AArch64SpeculationHardening.cpp Initial AArch64 SLH implementation. 2019-01-09 15:13:34 +00:00
AArch64StorePairSuppress.cpp [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operand 2018-11-28 12:00:20 +00:00
AArch64Subtarget.cpp [AArch64] Refactor the scheduling predicates (1/3) (NFC) 2018-11-26 21:47:28 +00:00
AArch64Subtarget.h [AArch64] Add new target feature to fuse arithmetic and logic operations 2019-01-14 23:54:36 +00:00
AArch64SystemOperands.td [AArch64] Move feature predctrl to predres 2019-01-09 11:24:15 +00:00
AArch64TargetMachine.cpp Introduce control flow speculation tracking pass for AArch64 2018-12-18 08:50:02 +00:00
AArch64TargetMachine.h
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AArch64TargetObjectFile.cpp [AArch64] DWARF: do not generate AT_location for thread local 2018-08-01 23:46:49 +00:00
AArch64TargetObjectFile.h Move TargetLoweringObjectFile from CodeGen to Target to fix layering 2018-03-23 23:58:19 +00:00
AArch64TargetTransformInfo.cpp [LV] Support vectorization of interleave-groups that require an epilog under 2018-10-31 09:57:56 +00:00
AArch64TargetTransformInfo.h [LV] Support vectorization of interleave-groups that require an epilog under 2018-10-31 09:57:56 +00:00
CMakeLists.txt Introduce control flow speculation tracking pass for AArch64 2018-12-18 08:50:02 +00:00
LLVMBuild.txt
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SVEInstrFormats.td Remove extra whitespace. NFC. (test commit) 2018-09-28 08:45:28 +00:00