forked from OSchip/llvm-project
4164 lines
303 KiB
C++
4164 lines
303 KiB
C++
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
|
|
// expected-no-diagnostics
|
|
#ifndef HEADER
|
|
#define HEADER
|
|
// Test host codegen.
|
|
// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
|
|
// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
|
|
// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2
|
|
// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
|
|
// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
|
|
// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4
|
|
|
|
// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
|
|
// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
|
|
// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
#ifdef CK1
|
|
|
|
int Gbla;
|
|
long long Gblb;
|
|
int &Gblc = Gbla;
|
|
|
|
int teams_argument_global_local(int a){
|
|
int comp = 1;
|
|
|
|
int la = 23;
|
|
float lc = 25.0;
|
|
|
|
#pragma omp target
|
|
#pragma omp teams
|
|
{
|
|
++comp;
|
|
}
|
|
|
|
#pragma omp target
|
|
{{{
|
|
#pragma omp teams
|
|
{
|
|
++comp;
|
|
}
|
|
}}}
|
|
|
|
|
|
#pragma omp target
|
|
#pragma omp teams num_teams(la)
|
|
{
|
|
++comp;
|
|
}
|
|
|
|
|
|
#pragma omp target
|
|
#pragma omp teams thread_limit(la)
|
|
{
|
|
++comp;
|
|
}
|
|
|
|
|
|
|
|
|
|
#pragma omp target
|
|
#pragma omp teams num_teams(Gbla+a) thread_limit(Gblb+(long long)lc)
|
|
{
|
|
++comp;
|
|
}
|
|
|
|
|
|
|
|
|
|
#pragma omp target
|
|
#pragma omp teams num_teams(Gblc+1) thread_limit(Gblc+2)
|
|
{
|
|
comp += Gblc;
|
|
}
|
|
|
|
return comp;
|
|
}
|
|
|
|
#endif // CK1
|
|
|
|
// Test host codegen.
|
|
// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9
|
|
// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
|
|
// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10
|
|
// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
|
|
// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
|
|
// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12
|
|
|
|
// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
|
|
// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
|
|
// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
#ifdef CK2
|
|
|
|
template <typename T>
|
|
struct SS{
|
|
T a;
|
|
float b;
|
|
};
|
|
|
|
SS<int> Gbla;
|
|
SS<long long> Gblb;
|
|
|
|
int teams_template_arg(void) {
|
|
int comp = 1;
|
|
|
|
SS<int> la;
|
|
SS<long long> lb;
|
|
|
|
|
|
|
|
|
|
#pragma omp target
|
|
#pragma omp teams num_teams(Gbla.a) thread_limit((long long)la.b)
|
|
{
|
|
++comp;
|
|
}
|
|
|
|
|
|
|
|
|
|
#pragma omp target
|
|
#pragma omp teams num_teams((long long)lb.b) thread_limit(Gblb.a)
|
|
{
|
|
++comp;
|
|
}
|
|
return comp;
|
|
}
|
|
#endif // CK2
|
|
|
|
// Test host codegen.
|
|
// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17
|
|
// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
|
|
// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18
|
|
// RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19
|
|
// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
|
|
// RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20
|
|
|
|
// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
|
|
// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
|
|
// RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
#ifdef CK3
|
|
|
|
|
|
template <typename T, int X, long long Y>
|
|
struct SS{
|
|
T a;
|
|
float b;
|
|
|
|
int foo(void) {
|
|
int comp = 1;
|
|
|
|
|
|
|
|
#pragma omp target
|
|
#pragma omp teams num_teams(a) thread_limit(X)
|
|
{
|
|
++comp;
|
|
}
|
|
|
|
|
|
|
|
#pragma omp target
|
|
#pragma omp teams num_teams(Y) thread_limit((int)b+X)
|
|
{
|
|
++comp;
|
|
}
|
|
return comp;
|
|
}
|
|
};
|
|
|
|
int teams_template_struct(void) {
|
|
SS<int, 123, 456> V;
|
|
return V.foo();
|
|
|
|
}
|
|
#endif // CK3
|
|
|
|
// Test target codegen - host bc file has to be created first.
|
|
// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
|
|
// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK25
|
|
// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
|
|
// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26
|
|
// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
|
|
// RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK27
|
|
// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
|
|
// RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28
|
|
|
|
// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
|
|
// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
|
|
// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
|
|
// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
|
|
// RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
|
|
#ifdef CK4
|
|
|
|
|
|
template <typename T>
|
|
int tmain(T argc) {
|
|
#pragma omp target
|
|
#pragma omp teams
|
|
argc = 0;
|
|
return 0;
|
|
}
|
|
|
|
int main (int argc, char **argv) {
|
|
#pragma omp target
|
|
#pragma omp teams
|
|
argc = 0;
|
|
return tmain(argv);
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif // CK4
|
|
|
|
// Test target codegen - host bc file has to be created first.
|
|
// RUN: %clang_cc1 -DCK5 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
|
|
// RUN: %clang_cc1 -DCK5 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK33
|
|
// RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
|
|
// RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK34
|
|
// RUN: %clang_cc1 -DCK5 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
|
|
// RUN: %clang_cc1 -DCK5 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK35
|
|
// RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
|
|
// RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK36
|
|
|
|
// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
|
|
// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
// RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
|
|
// RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
|
|
// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
// RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
|
|
// RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
|
|
// expected-no-diagnostics
|
|
#ifdef CK5
|
|
|
|
|
|
template <typename T>
|
|
int tmain(T argc) {
|
|
int a = 10;
|
|
int b = 5;
|
|
#pragma omp target
|
|
#pragma omp teams num_teams(a) thread_limit(b)
|
|
{
|
|
argc = 0;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int main (int argc, char **argv) {
|
|
int a = 20;
|
|
int b = 5;
|
|
#pragma omp target
|
|
#pragma omp teams num_teams(a) thread_limit(b)
|
|
{
|
|
argc = 0;
|
|
}
|
|
return tmain(argv);
|
|
}
|
|
|
|
|
|
|
|
#endif // CK5
|
|
|
|
// Test host codegen.
|
|
// RUN: %clang_cc1 -DCK6 -verify -fopenmp -fopenmp-version=50 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK41
|
|
// RUN: %clang_cc1 -DCK6 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
|
|
// RUN: %clang_cc1 -DCK6 -fopenmp-version=50 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK42
|
|
// RUN: %clang_cc1 -DCK6 -verify -fopenmp -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK43
|
|
// RUN: %clang_cc1 -DCK6 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
|
|
// RUN: %clang_cc1 -DCK6 -fopenmp -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK44
|
|
|
|
// RUN: %clang_cc1 -DCK6 -verify -fopenmp-version=50 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
// RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
|
|
// RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
// RUN: %clang_cc1 -DCK6 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
// RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
|
|
// RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
|
|
#ifdef CK6
|
|
|
|
void foo() {
|
|
#pragma omp teams
|
|
;
|
|
}
|
|
|
|
#endif // CK6
|
|
|
|
#endif
|
|
// CHECK1-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali
|
|
// CHECK1-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[COMP:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[LA:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[LC:%.*]] = alloca float, align 4
|
|
// CHECK1-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK1-NEXT: [[COMP_CASTED1:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK1-NEXT: [[LA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[COMP_CASTED9:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS11:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS12:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS13:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK1-NEXT: [[LA_CASTED16:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[COMP_CASTED18:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK1-NEXT: [[GBLA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[GBLB_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LC_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[COMP_CASTED28:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS30:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS31:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS32:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[GBLC_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[COMP_CASTED38:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK1-NEXT: [[_TMP43:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[_TMP45:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 1, i32* [[COMP]], align 4
|
|
// CHECK1-NEXT: store i32 23, i32* [[LA]], align 4
|
|
// CHECK1-NEXT: store float 2.500000e+01, float* [[LC]], align 4
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[COMP_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK1: omp_offload.failed:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31(i64 [[TMP1]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK1: omp_offload.cont:
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[COMP_CASTED1]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[COMP_CASTED1]], align 8
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP14]], align 8
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP16]], align 8
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP17]], align 8
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
|
|
// CHECK1: omp_offload.failed6:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37(i64 [[TMP12]]) #[[ATTR2]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT7]]
|
|
// CHECK1: omp_offload.cont7:
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[LA]], align 4
|
|
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[LA_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP22]], i32* [[CONV8]], align 4
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = load i64, i64* [[LA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK1-NEXT: [[CONV10:%.*]] = bitcast i64* [[COMP_CASTED9]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP24]], i32* [[CONV10]], align 4
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = load i64, i64* [[COMP_CASTED9]], align 8
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP23]], i64* [[TMP27]], align 8
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP23]], i64* [[TMP29]], align 8
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS13]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8
|
|
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP25]], i64* [[TMP34]], align 8
|
|
// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS13]], i64 0, i64 1
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP35]], align 8
|
|
// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP38:%.*]] = load i32, i32* [[LA]], align 4
|
|
// CHECK1-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46.region_id, i32 2, i8** [[TMP36]], i8** [[TMP37]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP38]], i32 0)
|
|
// CHECK1-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]
|
|
// CHECK1: omp_offload.failed14:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46(i64 [[TMP23]], i64 [[TMP25]]) #[[ATTR2]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT15]]
|
|
// CHECK1: omp_offload.cont15:
|
|
// CHECK1-NEXT: [[TMP41:%.*]] = load i32, i32* [[LA]], align 4
|
|
// CHECK1-NEXT: [[CONV17:%.*]] = bitcast i64* [[LA_CASTED16]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP41]], i32* [[CONV17]], align 4
|
|
// CHECK1-NEXT: [[TMP42:%.*]] = load i64, i64* [[LA_CASTED16]], align 8
|
|
// CHECK1-NEXT: [[TMP43:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK1-NEXT: [[CONV19:%.*]] = bitcast i64* [[COMP_CASTED18]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP43]], i32* [[CONV19]], align 4
|
|
// CHECK1-NEXT: [[TMP44:%.*]] = load i64, i64* [[COMP_CASTED18]], align 8
|
|
// CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP42]], i64* [[TMP46]], align 8
|
|
// CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP42]], i64* [[TMP48]], align 8
|
|
// CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP49]], align 8
|
|
// CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP44]], i64* [[TMP51]], align 8
|
|
// CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP44]], i64* [[TMP53]], align 8
|
|
// CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP54]], align 8
|
|
// CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP57:%.*]] = load i32, i32* [[LA]], align 4
|
|
// CHECK1-NEXT: [[TMP58:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP57]])
|
|
// CHECK1-NEXT: [[TMP59:%.*]] = icmp ne i32 [[TMP58]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP59]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
|
|
// CHECK1: omp_offload.failed23:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53(i64 [[TMP42]], i64 [[TMP44]]) #[[ATTR2]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT24]]
|
|
// CHECK1: omp_offload.cont24:
|
|
// CHECK1-NEXT: [[TMP60:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK1-NEXT: [[CONV25:%.*]] = bitcast i64* [[GBLA_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP60]], i32* [[CONV25]], align 4
|
|
// CHECK1-NEXT: [[TMP61:%.*]] = load i64, i64* [[GBLA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP62:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CONV26:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP62]], i32* [[CONV26]], align 4
|
|
// CHECK1-NEXT: [[TMP63:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP64:%.*]] = load i64, i64* @Gblb, align 8
|
|
// CHECK1-NEXT: store i64 [[TMP64]], i64* [[GBLB_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP65:%.*]] = load i64, i64* [[GBLB_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP66:%.*]] = load float, float* [[LC]], align 4
|
|
// CHECK1-NEXT: [[CONV27:%.*]] = bitcast i64* [[LC_CASTED]] to float*
|
|
// CHECK1-NEXT: store float [[TMP66]], float* [[CONV27]], align 4
|
|
// CHECK1-NEXT: [[TMP67:%.*]] = load i64, i64* [[LC_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP68:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK1-NEXT: [[CONV29:%.*]] = bitcast i64* [[COMP_CASTED28]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP68]], i32* [[CONV29]], align 4
|
|
// CHECK1-NEXT: [[TMP69:%.*]] = load i64, i64* [[COMP_CASTED28]], align 8
|
|
// CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP61]], i64* [[TMP71]], align 8
|
|
// CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP61]], i64* [[TMP73]], align 8
|
|
// CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP74]], align 8
|
|
// CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP63]], i64* [[TMP76]], align 8
|
|
// CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP63]], i64* [[TMP78]], align 8
|
|
// CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 1
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP79]], align 8
|
|
// CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP65]], i64* [[TMP81]], align 8
|
|
// CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP65]], i64* [[TMP83]], align 8
|
|
// CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 2
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP84]], align 8
|
|
// CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP67]], i64* [[TMP86]], align 8
|
|
// CHECK1-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP67]], i64* [[TMP88]], align 8
|
|
// CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 3
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP89]], align 8
|
|
// CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 4
|
|
// CHECK1-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP69]], i64* [[TMP91]], align 8
|
|
// CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 4
|
|
// CHECK1-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP69]], i64* [[TMP93]], align 8
|
|
// CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 4
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP94]], align 8
|
|
// CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP97:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK1-NEXT: [[TMP98:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP97]], [[TMP98]]
|
|
// CHECK1-NEXT: [[TMP99:%.*]] = load i64, i64* @Gblb, align 8
|
|
// CHECK1-NEXT: [[TMP100:%.*]] = load float, float* [[LC]], align 4
|
|
// CHECK1-NEXT: [[CONV33:%.*]] = fptosi float [[TMP100]] to i64
|
|
// CHECK1-NEXT: [[ADD34:%.*]] = add nsw i64 [[TMP99]], [[CONV33]]
|
|
// CHECK1-NEXT: [[TMP101:%.*]] = trunc i64 [[ADD34]] to i32
|
|
// CHECK1-NEXT: [[TMP102:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62.region_id, i32 5, i8** [[TMP95]], i8** [[TMP96]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 [[ADD]], i32 [[TMP101]])
|
|
// CHECK1-NEXT: [[TMP103:%.*]] = icmp ne i32 [[TMP102]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP103]], label [[OMP_OFFLOAD_FAILED35:%.*]], label [[OMP_OFFLOAD_CONT36:%.*]]
|
|
// CHECK1: omp_offload.failed35:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62(i64 [[TMP61]], i64 [[TMP63]], i64 [[TMP65]], i64 [[TMP67]], i64 [[TMP69]]) #[[ATTR2]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT36]]
|
|
// CHECK1: omp_offload.cont36:
|
|
// CHECK1-NEXT: [[TMP104:%.*]] = load i32*, i32** @Gblc, align 8
|
|
// CHECK1-NEXT: store i32* [[TMP104]], i32** [[TMP]], align 8
|
|
// CHECK1-NEXT: [[TMP105:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK1-NEXT: [[CONV37:%.*]] = bitcast i64* [[GBLC_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP105]], i32* [[CONV37]], align 4
|
|
// CHECK1-NEXT: [[TMP106:%.*]] = load i64, i64* [[GBLC_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP107:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK1-NEXT: [[CONV39:%.*]] = bitcast i64* [[COMP_CASTED38]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP107]], i32* [[CONV39]], align 4
|
|
// CHECK1-NEXT: [[TMP108:%.*]] = load i64, i64* [[COMP_CASTED38]], align 8
|
|
// CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP106]], i64* [[TMP110]], align 8
|
|
// CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP106]], i64* [[TMP112]], align 8
|
|
// CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP113]], align 8
|
|
// CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP108]], i64* [[TMP115]], align 8
|
|
// CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP108]], i64* [[TMP117]], align 8
|
|
// CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 1
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP118]], align 8
|
|
// CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP121:%.*]] = load i32*, i32** @Gblc, align 8
|
|
// CHECK1-NEXT: store i32* [[TMP121]], i32** [[_TMP43]], align 8
|
|
// CHECK1-NEXT: [[TMP122:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK1-NEXT: [[ADD44:%.*]] = add nsw i32 [[TMP122]], 1
|
|
// CHECK1-NEXT: [[TMP123:%.*]] = load i32*, i32** @Gblc, align 8
|
|
// CHECK1-NEXT: store i32* [[TMP123]], i32** [[_TMP45]], align 8
|
|
// CHECK1-NEXT: [[TMP124:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK1-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP124]], 2
|
|
// CHECK1-NEXT: [[TMP125:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71.region_id, i32 2, i8** [[TMP119]], i8** [[TMP120]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 [[ADD44]], i32 [[ADD46]])
|
|
// CHECK1-NEXT: [[TMP126:%.*]] = icmp ne i32 [[TMP125]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP126]], label [[OMP_OFFLOAD_FAILED47:%.*]], label [[OMP_OFFLOAD_CONT48:%.*]]
|
|
// CHECK1: omp_offload.failed47:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71(i64 [[TMP106]], i64 [[TMP108]]) #[[ATTR2]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT48]]
|
|
// CHECK1: omp_offload.cont48:
|
|
// CHECK1-NEXT: [[TMP127:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK1-NEXT: ret i32 [[TMP127]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31
|
|
// CHECK1-SAME: (i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK1-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37
|
|
// CHECK1-SAME: (i64 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK1-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46
|
|
// CHECK1-SAME: (i64 [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK1-NEXT: store i64 [[LA]], i64* [[LA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[CONV1]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK1-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53
|
|
// CHECK1-SAME: (i64 [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK1-NEXT: store i64 [[LA]], i64* [[LA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV1]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK1-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62
|
|
// CHECK1-SAME: (i64 [[GBLA:%.*]], i64 [[A:%.*]], i64 [[GBLB:%.*]], i64 [[LC:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[GBLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[GBLB_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LC_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK1-NEXT: store i64 [[GBLA]], i64* [[GBLA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[GBLB]], i64* [[GBLB_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[LC]], i64* [[LC_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[GBLA_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[LC_ADDR]] to float*
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[GBLB_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load float, float* [[CONV2]], align 8
|
|
// CHECK1-NEXT: [[CONV4:%.*]] = fptosi float [[TMP4]] to i64
|
|
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP3]], [[CONV4]]
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = trunc i64 [[ADD5]] to i32
|
|
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[TMP5]])
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[CONV3]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK1-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71
|
|
// CHECK1-SAME: (i64 [[GBLC:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[GBLC_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK1-NEXT: store i64 [[GBLC]], i64* [[GBLC_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[GBLC_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK1-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 2
|
|
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[ADD2]])
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32* [[CONV1]], i32* [[TMP3]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]], i32* nonnull align 4 dereferenceable(4) [[GBLC:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[GBLC_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[GBLC]], i32** [[GBLC_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[GBLC_ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]]
|
|
// CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali
|
|
// CHECK2-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[COMP:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[LA:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[LC:%.*]] = alloca float, align 4
|
|
// CHECK2-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[COMP_CASTED1:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[LA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[COMP_CASTED9:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS11:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS12:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS13:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK2-NEXT: [[LA_CASTED16:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[COMP_CASTED18:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK2-NEXT: [[GBLA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[GBLB_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[LC_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[COMP_CASTED28:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS30:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS31:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS32:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[GBLC_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[COMP_CASTED38:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK2-NEXT: [[_TMP43:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[_TMP45:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK2-NEXT: store i32 1, i32* [[COMP]], align 4
|
|
// CHECK2-NEXT: store i32 23, i32* [[LA]], align 4
|
|
// CHECK2-NEXT: store float 2.500000e+01, float* [[LC]], align 4
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[COMP_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP6]], align 8
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK2: omp_offload.failed:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31(i64 [[TMP1]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK2: omp_offload.cont:
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[COMP_CASTED1]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[COMP_CASTED1]], align 8
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP12]], i64* [[TMP14]], align 8
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP12]], i64* [[TMP16]], align 8
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP17]], align 8
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
|
|
// CHECK2: omp_offload.failed6:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37(i64 [[TMP12]]) #[[ATTR2]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT7]]
|
|
// CHECK2: omp_offload.cont7:
|
|
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[LA]], align 4
|
|
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[LA_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP22]], i32* [[CONV8]], align 4
|
|
// CHECK2-NEXT: [[TMP23:%.*]] = load i64, i64* [[LA_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK2-NEXT: [[CONV10:%.*]] = bitcast i64* [[COMP_CASTED9]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP24]], i32* [[CONV10]], align 4
|
|
// CHECK2-NEXT: [[TMP25:%.*]] = load i64, i64* [[COMP_CASTED9]], align 8
|
|
// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP23]], i64* [[TMP27]], align 8
|
|
// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP23]], i64* [[TMP29]], align 8
|
|
// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS13]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP30]], align 8
|
|
// CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8
|
|
// CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP25]], i64* [[TMP34]], align 8
|
|
// CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS13]], i64 0, i64 1
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP35]], align 8
|
|
// CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP38:%.*]] = load i32, i32* [[LA]], align 4
|
|
// CHECK2-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46.region_id, i32 2, i8** [[TMP36]], i8** [[TMP37]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP38]], i32 0)
|
|
// CHECK2-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]
|
|
// CHECK2: omp_offload.failed14:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46(i64 [[TMP23]], i64 [[TMP25]]) #[[ATTR2]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT15]]
|
|
// CHECK2: omp_offload.cont15:
|
|
// CHECK2-NEXT: [[TMP41:%.*]] = load i32, i32* [[LA]], align 4
|
|
// CHECK2-NEXT: [[CONV17:%.*]] = bitcast i64* [[LA_CASTED16]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP41]], i32* [[CONV17]], align 4
|
|
// CHECK2-NEXT: [[TMP42:%.*]] = load i64, i64* [[LA_CASTED16]], align 8
|
|
// CHECK2-NEXT: [[TMP43:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK2-NEXT: [[CONV19:%.*]] = bitcast i64* [[COMP_CASTED18]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP43]], i32* [[CONV19]], align 4
|
|
// CHECK2-NEXT: [[TMP44:%.*]] = load i64, i64* [[COMP_CASTED18]], align 8
|
|
// CHECK2-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP42]], i64* [[TMP46]], align 8
|
|
// CHECK2-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP42]], i64* [[TMP48]], align 8
|
|
// CHECK2-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP49]], align 8
|
|
// CHECK2-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP44]], i64* [[TMP51]], align 8
|
|
// CHECK2-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP44]], i64* [[TMP53]], align 8
|
|
// CHECK2-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP54]], align 8
|
|
// CHECK2-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP57:%.*]] = load i32, i32* [[LA]], align 4
|
|
// CHECK2-NEXT: [[TMP58:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP57]])
|
|
// CHECK2-NEXT: [[TMP59:%.*]] = icmp ne i32 [[TMP58]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP59]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
|
|
// CHECK2: omp_offload.failed23:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53(i64 [[TMP42]], i64 [[TMP44]]) #[[ATTR2]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT24]]
|
|
// CHECK2: omp_offload.cont24:
|
|
// CHECK2-NEXT: [[TMP60:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK2-NEXT: [[CONV25:%.*]] = bitcast i64* [[GBLA_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP60]], i32* [[CONV25]], align 4
|
|
// CHECK2-NEXT: [[TMP61:%.*]] = load i64, i64* [[GBLA_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP62:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CONV26:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP62]], i32* [[CONV26]], align 4
|
|
// CHECK2-NEXT: [[TMP63:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP64:%.*]] = load i64, i64* @Gblb, align 8
|
|
// CHECK2-NEXT: store i64 [[TMP64]], i64* [[GBLB_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP65:%.*]] = load i64, i64* [[GBLB_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP66:%.*]] = load float, float* [[LC]], align 4
|
|
// CHECK2-NEXT: [[CONV27:%.*]] = bitcast i64* [[LC_CASTED]] to float*
|
|
// CHECK2-NEXT: store float [[TMP66]], float* [[CONV27]], align 4
|
|
// CHECK2-NEXT: [[TMP67:%.*]] = load i64, i64* [[LC_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP68:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK2-NEXT: [[CONV29:%.*]] = bitcast i64* [[COMP_CASTED28]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP68]], i32* [[CONV29]], align 4
|
|
// CHECK2-NEXT: [[TMP69:%.*]] = load i64, i64* [[COMP_CASTED28]], align 8
|
|
// CHECK2-NEXT: [[TMP70:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP61]], i64* [[TMP71]], align 8
|
|
// CHECK2-NEXT: [[TMP72:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP61]], i64* [[TMP73]], align 8
|
|
// CHECK2-NEXT: [[TMP74:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP74]], align 8
|
|
// CHECK2-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP63]], i64* [[TMP76]], align 8
|
|
// CHECK2-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP63]], i64* [[TMP78]], align 8
|
|
// CHECK2-NEXT: [[TMP79:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 1
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP79]], align 8
|
|
// CHECK2-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP65]], i64* [[TMP81]], align 8
|
|
// CHECK2-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP65]], i64* [[TMP83]], align 8
|
|
// CHECK2-NEXT: [[TMP84:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 2
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP84]], align 8
|
|
// CHECK2-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 3
|
|
// CHECK2-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP67]], i64* [[TMP86]], align 8
|
|
// CHECK2-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 3
|
|
// CHECK2-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP67]], i64* [[TMP88]], align 8
|
|
// CHECK2-NEXT: [[TMP89:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 3
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP89]], align 8
|
|
// CHECK2-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 4
|
|
// CHECK2-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP69]], i64* [[TMP91]], align 8
|
|
// CHECK2-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 4
|
|
// CHECK2-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP69]], i64* [[TMP93]], align 8
|
|
// CHECK2-NEXT: [[TMP94:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 4
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP94]], align 8
|
|
// CHECK2-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP96:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP97:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK2-NEXT: [[TMP98:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP97]], [[TMP98]]
|
|
// CHECK2-NEXT: [[TMP99:%.*]] = load i64, i64* @Gblb, align 8
|
|
// CHECK2-NEXT: [[TMP100:%.*]] = load float, float* [[LC]], align 4
|
|
// CHECK2-NEXT: [[CONV33:%.*]] = fptosi float [[TMP100]] to i64
|
|
// CHECK2-NEXT: [[ADD34:%.*]] = add nsw i64 [[TMP99]], [[CONV33]]
|
|
// CHECK2-NEXT: [[TMP101:%.*]] = trunc i64 [[ADD34]] to i32
|
|
// CHECK2-NEXT: [[TMP102:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62.region_id, i32 5, i8** [[TMP95]], i8** [[TMP96]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 [[ADD]], i32 [[TMP101]])
|
|
// CHECK2-NEXT: [[TMP103:%.*]] = icmp ne i32 [[TMP102]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP103]], label [[OMP_OFFLOAD_FAILED35:%.*]], label [[OMP_OFFLOAD_CONT36:%.*]]
|
|
// CHECK2: omp_offload.failed35:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62(i64 [[TMP61]], i64 [[TMP63]], i64 [[TMP65]], i64 [[TMP67]], i64 [[TMP69]]) #[[ATTR2]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT36]]
|
|
// CHECK2: omp_offload.cont36:
|
|
// CHECK2-NEXT: [[TMP104:%.*]] = load i32*, i32** @Gblc, align 8
|
|
// CHECK2-NEXT: store i32* [[TMP104]], i32** [[TMP]], align 8
|
|
// CHECK2-NEXT: [[TMP105:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK2-NEXT: [[CONV37:%.*]] = bitcast i64* [[GBLC_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP105]], i32* [[CONV37]], align 4
|
|
// CHECK2-NEXT: [[TMP106:%.*]] = load i64, i64* [[GBLC_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP107:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK2-NEXT: [[CONV39:%.*]] = bitcast i64* [[COMP_CASTED38]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP107]], i32* [[CONV39]], align 4
|
|
// CHECK2-NEXT: [[TMP108:%.*]] = load i64, i64* [[COMP_CASTED38]], align 8
|
|
// CHECK2-NEXT: [[TMP109:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP106]], i64* [[TMP110]], align 8
|
|
// CHECK2-NEXT: [[TMP111:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP106]], i64* [[TMP112]], align 8
|
|
// CHECK2-NEXT: [[TMP113:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP113]], align 8
|
|
// CHECK2-NEXT: [[TMP114:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP108]], i64* [[TMP115]], align 8
|
|
// CHECK2-NEXT: [[TMP116:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP108]], i64* [[TMP117]], align 8
|
|
// CHECK2-NEXT: [[TMP118:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 1
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP118]], align 8
|
|
// CHECK2-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP120:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP121:%.*]] = load i32*, i32** @Gblc, align 8
|
|
// CHECK2-NEXT: store i32* [[TMP121]], i32** [[_TMP43]], align 8
|
|
// CHECK2-NEXT: [[TMP122:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK2-NEXT: [[ADD44:%.*]] = add nsw i32 [[TMP122]], 1
|
|
// CHECK2-NEXT: [[TMP123:%.*]] = load i32*, i32** @Gblc, align 8
|
|
// CHECK2-NEXT: store i32* [[TMP123]], i32** [[_TMP45]], align 8
|
|
// CHECK2-NEXT: [[TMP124:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK2-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP124]], 2
|
|
// CHECK2-NEXT: [[TMP125:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71.region_id, i32 2, i8** [[TMP119]], i8** [[TMP120]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 [[ADD44]], i32 [[ADD46]])
|
|
// CHECK2-NEXT: [[TMP126:%.*]] = icmp ne i32 [[TMP125]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP126]], label [[OMP_OFFLOAD_FAILED47:%.*]], label [[OMP_OFFLOAD_CONT48:%.*]]
|
|
// CHECK2: omp_offload.failed47:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71(i64 [[TMP106]], i64 [[TMP108]]) #[[ATTR2]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT48]]
|
|
// CHECK2: omp_offload.cont48:
|
|
// CHECK2-NEXT: [[TMP127:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK2-NEXT: ret i32 [[TMP127]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31
|
|
// CHECK2-SAME: (i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK2-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37
|
|
// CHECK2-SAME: (i64 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK2-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46
|
|
// CHECK2-SAME: (i64 [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK2-NEXT: store i64 [[LA]], i64* [[LA_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[CONV1]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK2-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53
|
|
// CHECK2-SAME: (i64 [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK2-NEXT: store i64 [[LA]], i64* [[LA_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV1]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK2-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62
|
|
// CHECK2-SAME: (i64 [[GBLA:%.*]], i64 [[A:%.*]], i64 [[GBLB:%.*]], i64 [[LC:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[GBLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[GBLB_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[LC_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK2-NEXT: store i64 [[GBLA]], i64* [[GBLA_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[GBLB]], i64* [[GBLB_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[LC]], i64* [[LC_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[GBLA_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[LC_ADDR]] to float*
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[GBLB_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load float, float* [[CONV2]], align 8
|
|
// CHECK2-NEXT: [[CONV4:%.*]] = fptosi float [[TMP4]] to i64
|
|
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP3]], [[CONV4]]
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = trunc i64 [[ADD5]] to i32
|
|
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[TMP5]])
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[CONV3]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK2-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71
|
|
// CHECK2-SAME: (i64 [[GBLC:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[GBLC_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK2-NEXT: store i64 [[GBLC]], i64* [[GBLC_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[GBLC_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK2-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 2
|
|
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[ADD2]])
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32* [[CONV1]], i32* [[TMP3]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]], i32* nonnull align 4 dereferenceable(4) [[GBLC:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[GBLC_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[GBLC]], i32** [[GBLC_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[GBLC_ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]]
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK2-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali
|
|
// CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[COMP:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LA:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LC:%.*]] = alloca float, align 4
|
|
// CHECK3-NEXT: [[COMP_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[COMP_CASTED1:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[LA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[COMP_CASTED7:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK3-NEXT: [[LA_CASTED13:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[COMP_CASTED14:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS15:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS16:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS17:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK3-NEXT: [[GBLA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LC_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[COMP_CASTED20:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[GBLC_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[COMP_CASTED28:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS29:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS30:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS31:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK3-NEXT: [[_TMP32:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[_TMP34:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 1, i32* [[COMP]], align 4
|
|
// CHECK3-NEXT: store i32 23, i32* [[LA]], align 4
|
|
// CHECK3-NEXT: store float 2.500000e+01, float* [[LC]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[COMP_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP6]], align 4
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK3: omp_offload.failed:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31(i32 [[TMP1]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK3: omp_offload.cont:
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP11]], i32* [[COMP_CASTED1]], align 4
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[COMP_CASTED1]], align 4
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP17]], align 4
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
|
|
// CHECK3: omp_offload.failed5:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37(i32 [[TMP12]]) #[[ATTR2]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT6]]
|
|
// CHECK3: omp_offload.cont6:
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[LA]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP22]], i32* [[LA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[LA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP24]], i32* [[COMP_CASTED7]], align 4
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[COMP_CASTED7]], align 4
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP23]], i32* [[TMP27]], align 4
|
|
// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP23]], i32* [[TMP29]], align 4
|
|
// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4
|
|
// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP25]], i32* [[TMP32]], align 4
|
|
// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP25]], i32* [[TMP34]], align 4
|
|
// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP35]], align 4
|
|
// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP38:%.*]] = load i32, i32* [[LA]], align 4
|
|
// CHECK3-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46.region_id, i32 2, i8** [[TMP36]], i8** [[TMP37]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP38]], i32 0)
|
|
// CHECK3-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]]
|
|
// CHECK3: omp_offload.failed11:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR2]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT12]]
|
|
// CHECK3: omp_offload.cont12:
|
|
// CHECK3-NEXT: [[TMP41:%.*]] = load i32, i32* [[LA]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP41]], i32* [[LA_CASTED13]], align 4
|
|
// CHECK3-NEXT: [[TMP42:%.*]] = load i32, i32* [[LA_CASTED13]], align 4
|
|
// CHECK3-NEXT: [[TMP43:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP43]], i32* [[COMP_CASTED14]], align 4
|
|
// CHECK3-NEXT: [[TMP44:%.*]] = load i32, i32* [[COMP_CASTED14]], align 4
|
|
// CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP42]], i32* [[TMP46]], align 4
|
|
// CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP42]], i32* [[TMP48]], align 4
|
|
// CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP49]], align 4
|
|
// CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP44]], i32* [[TMP51]], align 4
|
|
// CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP44]], i32* [[TMP53]], align 4
|
|
// CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP54]], align 4
|
|
// CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP57:%.*]] = load i32, i32* [[LA]], align 4
|
|
// CHECK3-NEXT: [[TMP58:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP57]])
|
|
// CHECK3-NEXT: [[TMP59:%.*]] = icmp ne i32 [[TMP58]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP59]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]
|
|
// CHECK3: omp_offload.failed18:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53(i32 [[TMP42]], i32 [[TMP44]]) #[[ATTR2]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT19]]
|
|
// CHECK3: omp_offload.cont19:
|
|
// CHECK3-NEXT: [[TMP60:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK3-NEXT: store i32 [[TMP60]], i32* [[GBLA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP61:%.*]] = load i32, i32* [[GBLA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP62:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP62]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP63:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP64:%.*]] = load float, float* [[LC]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[LC_CASTED]] to float*
|
|
// CHECK3-NEXT: store float [[TMP64]], float* [[CONV]], align 4
|
|
// CHECK3-NEXT: [[TMP65:%.*]] = load i32, i32* [[LC_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP66:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP66]], i32* [[COMP_CASTED20]], align 4
|
|
// CHECK3-NEXT: [[TMP67:%.*]] = load i32, i32* [[COMP_CASTED20]], align 4
|
|
// CHECK3-NEXT: [[TMP68:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP61]], i32* [[TMP69]], align 4
|
|
// CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP61]], i32* [[TMP71]], align 4
|
|
// CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP72]], align 4
|
|
// CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP63]], i32* [[TMP74]], align 4
|
|
// CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP63]], i32* [[TMP76]], align 4
|
|
// CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP77]], align 4
|
|
// CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64**
|
|
// CHECK3-NEXT: store i64* @Gblb, i64** [[TMP79]], align 4
|
|
// CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64**
|
|
// CHECK3-NEXT: store i64* @Gblb, i64** [[TMP81]], align 4
|
|
// CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP82]], align 4
|
|
// CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3
|
|
// CHECK3-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP65]], i32* [[TMP84]], align 4
|
|
// CHECK3-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3
|
|
// CHECK3-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP65]], i32* [[TMP86]], align 4
|
|
// CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 3
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP87]], align 4
|
|
// CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 4
|
|
// CHECK3-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP67]], i32* [[TMP89]], align 4
|
|
// CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 4
|
|
// CHECK3-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP67]], i32* [[TMP91]], align 4
|
|
// CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 4
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP92]], align 4
|
|
// CHECK3-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP94:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP95:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK3-NEXT: [[TMP96:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP95]], [[TMP96]]
|
|
// CHECK3-NEXT: [[TMP97:%.*]] = load i64, i64* @Gblb, align 8
|
|
// CHECK3-NEXT: [[TMP98:%.*]] = load float, float* [[LC]], align 4
|
|
// CHECK3-NEXT: [[CONV24:%.*]] = fptosi float [[TMP98]] to i64
|
|
// CHECK3-NEXT: [[ADD25:%.*]] = add nsw i64 [[TMP97]], [[CONV24]]
|
|
// CHECK3-NEXT: [[TMP99:%.*]] = trunc i64 [[ADD25]] to i32
|
|
// CHECK3-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62.region_id, i32 5, i8** [[TMP93]], i8** [[TMP94]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 [[ADD]], i32 [[TMP99]])
|
|
// CHECK3-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED26:%.*]], label [[OMP_OFFLOAD_CONT27:%.*]]
|
|
// CHECK3: omp_offload.failed26:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62(i32 [[TMP61]], i32 [[TMP63]], i64* @Gblb, i32 [[TMP65]], i32 [[TMP67]]) #[[ATTR2]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT27]]
|
|
// CHECK3: omp_offload.cont27:
|
|
// CHECK3-NEXT: [[TMP102:%.*]] = load i32*, i32** @Gblc, align 4
|
|
// CHECK3-NEXT: store i32* [[TMP102]], i32** [[TMP]], align 4
|
|
// CHECK3-NEXT: [[TMP103:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK3-NEXT: store i32 [[TMP103]], i32* [[GBLC_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP104:%.*]] = load i32, i32* [[GBLC_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP105:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP105]], i32* [[COMP_CASTED28]], align 4
|
|
// CHECK3-NEXT: [[TMP106:%.*]] = load i32, i32* [[COMP_CASTED28]], align 4
|
|
// CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP104]], i32* [[TMP108]], align 4
|
|
// CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP104]], i32* [[TMP110]], align 4
|
|
// CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP111]], align 4
|
|
// CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP106]], i32* [[TMP113]], align 4
|
|
// CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP106]], i32* [[TMP115]], align 4
|
|
// CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP116]], align 4
|
|
// CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP119:%.*]] = load i32*, i32** @Gblc, align 4
|
|
// CHECK3-NEXT: store i32* [[TMP119]], i32** [[_TMP32]], align 4
|
|
// CHECK3-NEXT: [[TMP120:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK3-NEXT: [[ADD33:%.*]] = add nsw i32 [[TMP120]], 1
|
|
// CHECK3-NEXT: [[TMP121:%.*]] = load i32*, i32** @Gblc, align 4
|
|
// CHECK3-NEXT: store i32* [[TMP121]], i32** [[_TMP34]], align 4
|
|
// CHECK3-NEXT: [[TMP122:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK3-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP122]], 2
|
|
// CHECK3-NEXT: [[TMP123:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71.region_id, i32 2, i8** [[TMP117]], i8** [[TMP118]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 [[ADD33]], i32 [[ADD35]])
|
|
// CHECK3-NEXT: [[TMP124:%.*]] = icmp ne i32 [[TMP123]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP124]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]]
|
|
// CHECK3: omp_offload.failed36:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71(i32 [[TMP104]], i32 [[TMP106]]) #[[ATTR2]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT37]]
|
|
// CHECK3: omp_offload.cont37:
|
|
// CHECK3-NEXT: [[TMP125:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK3-NEXT: ret i32 [[TMP125]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31
|
|
// CHECK3-SAME: (i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK3-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37
|
|
// CHECK3-SAME: (i32 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK3-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46
|
|
// CHECK3-SAME: (i32 [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[LA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK3-NEXT: store i32 [[LA]], i32* [[LA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[LA_ADDR]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK3-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53
|
|
// CHECK3-SAME: (i32 [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[LA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK3-NEXT: store i32 [[LA]], i32* [[LA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[LA_ADDR]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK3-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62
|
|
// CHECK3-SAME: (i32 [[GBLA:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[GBLB:%.*]], i32 [[LC:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[GBLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[GBLB_ADDR:%.*]] = alloca i64*, align 4
|
|
// CHECK3-NEXT: [[LC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[GBLB1:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK3-NEXT: store i32 [[GBLA]], i32* [[GBLA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i64* [[GBLB]], i64** [[GBLB_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[LC]], i32* [[LC_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i64*, i64** [[GBLB_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[LC_ADDR]] to float*
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i64, i64* [[TMP1]], align 8
|
|
// CHECK3-NEXT: store i64 [[TMP2]], i64* [[GBLB1]], align 8
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[GBLA_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP4]]
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[GBLB1]], align 8
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load float, float* [[CONV]], align 4
|
|
// CHECK3-NEXT: [[CONV2:%.*]] = fptosi float [[TMP6]] to i64
|
|
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i64 [[TMP5]], [[CONV2]]
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = trunc i64 [[ADD3]] to i32
|
|
// CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[TMP7]])
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK3-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71
|
|
// CHECK3-SAME: (i32 [[GBLC:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[GBLC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK3-NEXT: store i32 [[GBLC]], i32* [[GBLC_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[GBLC_ADDR]], i32** [[TMP]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], 2
|
|
// CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[ADD1]])
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]], i32* [[TMP3]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]], i32* nonnull align 4 dereferenceable(4) [[GBLC:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[GBLC_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[GBLC]], i32** [[GBLC_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[GBLC_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]]
|
|
// CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali
|
|
// CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[COMP:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[LA:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[LC:%.*]] = alloca float, align 4
|
|
// CHECK4-NEXT: [[COMP_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[COMP_CASTED1:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[LA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[COMP_CASTED7:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK4-NEXT: [[LA_CASTED13:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[COMP_CASTED14:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS15:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS16:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS17:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK4-NEXT: [[GBLA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[LC_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[COMP_CASTED20:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[GBLC_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[COMP_CASTED28:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS29:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS30:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS31:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK4-NEXT: [[_TMP32:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[_TMP34:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 1, i32* [[COMP]], align 4
|
|
// CHECK4-NEXT: store i32 23, i32* [[LA]], align 4
|
|
// CHECK4-NEXT: store float 2.500000e+01, float* [[LC]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[COMP_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP6]], align 4
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK4: omp_offload.failed:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31(i32 [[TMP1]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK4: omp_offload.cont:
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP11]], i32* [[COMP_CASTED1]], align 4
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[COMP_CASTED1]], align 4
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP17]], align 4
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
|
|
// CHECK4: omp_offload.failed5:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37(i32 [[TMP12]]) #[[ATTR2]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT6]]
|
|
// CHECK4: omp_offload.cont6:
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[LA]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP22]], i32* [[LA_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[LA_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP24]], i32* [[COMP_CASTED7]], align 4
|
|
// CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[COMP_CASTED7]], align 4
|
|
// CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP23]], i32* [[TMP27]], align 4
|
|
// CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP23]], i32* [[TMP29]], align 4
|
|
// CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP30]], align 4
|
|
// CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP25]], i32* [[TMP32]], align 4
|
|
// CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP25]], i32* [[TMP34]], align 4
|
|
// CHECK4-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP35]], align 4
|
|
// CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP38:%.*]] = load i32, i32* [[LA]], align 4
|
|
// CHECK4-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46.region_id, i32 2, i8** [[TMP36]], i8** [[TMP37]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP38]], i32 0)
|
|
// CHECK4-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]]
|
|
// CHECK4: omp_offload.failed11:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR2]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT12]]
|
|
// CHECK4: omp_offload.cont12:
|
|
// CHECK4-NEXT: [[TMP41:%.*]] = load i32, i32* [[LA]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP41]], i32* [[LA_CASTED13]], align 4
|
|
// CHECK4-NEXT: [[TMP42:%.*]] = load i32, i32* [[LA_CASTED13]], align 4
|
|
// CHECK4-NEXT: [[TMP43:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP43]], i32* [[COMP_CASTED14]], align 4
|
|
// CHECK4-NEXT: [[TMP44:%.*]] = load i32, i32* [[COMP_CASTED14]], align 4
|
|
// CHECK4-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP42]], i32* [[TMP46]], align 4
|
|
// CHECK4-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP42]], i32* [[TMP48]], align 4
|
|
// CHECK4-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP49]], align 4
|
|
// CHECK4-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP44]], i32* [[TMP51]], align 4
|
|
// CHECK4-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP44]], i32* [[TMP53]], align 4
|
|
// CHECK4-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP54]], align 4
|
|
// CHECK4-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP57:%.*]] = load i32, i32* [[LA]], align 4
|
|
// CHECK4-NEXT: [[TMP58:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP57]])
|
|
// CHECK4-NEXT: [[TMP59:%.*]] = icmp ne i32 [[TMP58]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP59]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]
|
|
// CHECK4: omp_offload.failed18:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53(i32 [[TMP42]], i32 [[TMP44]]) #[[ATTR2]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT19]]
|
|
// CHECK4: omp_offload.cont19:
|
|
// CHECK4-NEXT: [[TMP60:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK4-NEXT: store i32 [[TMP60]], i32* [[GBLA_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP61:%.*]] = load i32, i32* [[GBLA_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP62:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP62]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP63:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP64:%.*]] = load float, float* [[LC]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[LC_CASTED]] to float*
|
|
// CHECK4-NEXT: store float [[TMP64]], float* [[CONV]], align 4
|
|
// CHECK4-NEXT: [[TMP65:%.*]] = load i32, i32* [[LC_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP66:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP66]], i32* [[COMP_CASTED20]], align 4
|
|
// CHECK4-NEXT: [[TMP67:%.*]] = load i32, i32* [[COMP_CASTED20]], align 4
|
|
// CHECK4-NEXT: [[TMP68:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP61]], i32* [[TMP69]], align 4
|
|
// CHECK4-NEXT: [[TMP70:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP61]], i32* [[TMP71]], align 4
|
|
// CHECK4-NEXT: [[TMP72:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP72]], align 4
|
|
// CHECK4-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP63]], i32* [[TMP74]], align 4
|
|
// CHECK4-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP63]], i32* [[TMP76]], align 4
|
|
// CHECK4-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP77]], align 4
|
|
// CHECK4-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64**
|
|
// CHECK4-NEXT: store i64* @Gblb, i64** [[TMP79]], align 4
|
|
// CHECK4-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64**
|
|
// CHECK4-NEXT: store i64* @Gblb, i64** [[TMP81]], align 4
|
|
// CHECK4-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 2
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP82]], align 4
|
|
// CHECK4-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3
|
|
// CHECK4-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP65]], i32* [[TMP84]], align 4
|
|
// CHECK4-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3
|
|
// CHECK4-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP65]], i32* [[TMP86]], align 4
|
|
// CHECK4-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 3
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP87]], align 4
|
|
// CHECK4-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 4
|
|
// CHECK4-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP67]], i32* [[TMP89]], align 4
|
|
// CHECK4-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 4
|
|
// CHECK4-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP67]], i32* [[TMP91]], align 4
|
|
// CHECK4-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 4
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP92]], align 4
|
|
// CHECK4-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP94:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP95:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK4-NEXT: [[TMP96:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP95]], [[TMP96]]
|
|
// CHECK4-NEXT: [[TMP97:%.*]] = load i64, i64* @Gblb, align 8
|
|
// CHECK4-NEXT: [[TMP98:%.*]] = load float, float* [[LC]], align 4
|
|
// CHECK4-NEXT: [[CONV24:%.*]] = fptosi float [[TMP98]] to i64
|
|
// CHECK4-NEXT: [[ADD25:%.*]] = add nsw i64 [[TMP97]], [[CONV24]]
|
|
// CHECK4-NEXT: [[TMP99:%.*]] = trunc i64 [[ADD25]] to i32
|
|
// CHECK4-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62.region_id, i32 5, i8** [[TMP93]], i8** [[TMP94]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 [[ADD]], i32 [[TMP99]])
|
|
// CHECK4-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED26:%.*]], label [[OMP_OFFLOAD_CONT27:%.*]]
|
|
// CHECK4: omp_offload.failed26:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62(i32 [[TMP61]], i32 [[TMP63]], i64* @Gblb, i32 [[TMP65]], i32 [[TMP67]]) #[[ATTR2]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT27]]
|
|
// CHECK4: omp_offload.cont27:
|
|
// CHECK4-NEXT: [[TMP102:%.*]] = load i32*, i32** @Gblc, align 4
|
|
// CHECK4-NEXT: store i32* [[TMP102]], i32** [[TMP]], align 4
|
|
// CHECK4-NEXT: [[TMP103:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK4-NEXT: store i32 [[TMP103]], i32* [[GBLC_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP104:%.*]] = load i32, i32* [[GBLC_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP105:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP105]], i32* [[COMP_CASTED28]], align 4
|
|
// CHECK4-NEXT: [[TMP106:%.*]] = load i32, i32* [[COMP_CASTED28]], align 4
|
|
// CHECK4-NEXT: [[TMP107:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP104]], i32* [[TMP108]], align 4
|
|
// CHECK4-NEXT: [[TMP109:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP104]], i32* [[TMP110]], align 4
|
|
// CHECK4-NEXT: [[TMP111:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP111]], align 4
|
|
// CHECK4-NEXT: [[TMP112:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP106]], i32* [[TMP113]], align 4
|
|
// CHECK4-NEXT: [[TMP114:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP106]], i32* [[TMP115]], align 4
|
|
// CHECK4-NEXT: [[TMP116:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP116]], align 4
|
|
// CHECK4-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP118:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP119:%.*]] = load i32*, i32** @Gblc, align 4
|
|
// CHECK4-NEXT: store i32* [[TMP119]], i32** [[_TMP32]], align 4
|
|
// CHECK4-NEXT: [[TMP120:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK4-NEXT: [[ADD33:%.*]] = add nsw i32 [[TMP120]], 1
|
|
// CHECK4-NEXT: [[TMP121:%.*]] = load i32*, i32** @Gblc, align 4
|
|
// CHECK4-NEXT: store i32* [[TMP121]], i32** [[_TMP34]], align 4
|
|
// CHECK4-NEXT: [[TMP122:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK4-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP122]], 2
|
|
// CHECK4-NEXT: [[TMP123:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71.region_id, i32 2, i8** [[TMP117]], i8** [[TMP118]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 [[ADD33]], i32 [[ADD35]])
|
|
// CHECK4-NEXT: [[TMP124:%.*]] = icmp ne i32 [[TMP123]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP124]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]]
|
|
// CHECK4: omp_offload.failed36:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71(i32 [[TMP104]], i32 [[TMP106]]) #[[ATTR2]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT37]]
|
|
// CHECK4: omp_offload.cont37:
|
|
// CHECK4-NEXT: [[TMP125:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK4-NEXT: ret i32 [[TMP125]]
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31
|
|
// CHECK4-SAME: (i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK4-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37
|
|
// CHECK4-SAME: (i32 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK4-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46
|
|
// CHECK4-SAME: (i32 [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[LA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK4-NEXT: store i32 [[LA]], i32* [[LA_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[LA_ADDR]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK4-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53
|
|
// CHECK4-SAME: (i32 [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[LA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK4-NEXT: store i32 [[LA]], i32* [[LA_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[LA_ADDR]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK4-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62
|
|
// CHECK4-SAME: (i32 [[GBLA:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[GBLB:%.*]], i32 [[LC:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[GBLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[GBLB_ADDR:%.*]] = alloca i64*, align 4
|
|
// CHECK4-NEXT: [[LC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[GBLB1:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK4-NEXT: store i32 [[GBLA]], i32* [[GBLA_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i64* [[GBLB]], i64** [[GBLB_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[LC]], i32* [[LC_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i64*, i64** [[GBLB_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[LC_ADDR]] to float*
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i64, i64* [[TMP1]], align 8
|
|
// CHECK4-NEXT: store i64 [[TMP2]], i64* [[GBLB1]], align 8
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[GBLA_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP4]]
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[GBLB1]], align 8
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load float, float* [[CONV]], align 4
|
|
// CHECK4-NEXT: [[CONV2:%.*]] = fptosi float [[TMP6]] to i64
|
|
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i64 [[TMP5]], [[CONV2]]
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = trunc i64 [[ADD3]] to i32
|
|
// CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[TMP7]])
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK4-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71
|
|
// CHECK4-SAME: (i32 [[GBLC:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[GBLC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK4-NEXT: store i32 [[GBLC]], i32* [[GBLC_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[GBLC_ADDR]], i32** [[TMP]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], 2
|
|
// CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[ADD1]])
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]], i32* [[TMP3]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]], i32* nonnull align 4 dereferenceable(4) [[GBLC:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[GBLC_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[GBLC]], i32** [[GBLC_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[GBLC_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* @Gbla, align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]]
|
|
// CHECK4-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK4-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@_Z18teams_template_argv
|
|
// CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[COMP:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
|
|
// CHECK9-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 8
|
|
// CHECK9-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK9-NEXT: [[COMP_CASTED2:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK9-NEXT: store i32 1, i32* [[COMP]], align 4
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_CASTED]] to i32*
|
|
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[COMP_CASTED]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS**
|
|
// CHECK9-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP3]], align 8
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to %struct.SS**
|
|
// CHECK9-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP5]], align 8
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK9-NEXT: store i8* null, i8** [[TMP6]], align 8
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to %struct.SS**
|
|
// CHECK9-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP8]], align 8
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS**
|
|
// CHECK9-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP10]], align 8
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8
|
|
// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
|
|
// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8
|
|
// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK9-NEXT: store i8* null, i8** [[TMP16]], align 8
|
|
// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SS]], %struct.SS* @Gbla, i32 0, i32 0), align 4
|
|
// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[LA]], i32 0, i32 1
|
|
// CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[B]], align 4
|
|
// CHECK9-NEXT: [[CONV1:%.*]] = fptosi float [[TMP20]] to i64
|
|
// CHECK9-NEXT: [[TMP21:%.*]] = trunc i64 [[CONV1]] to i32
|
|
// CHECK9-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116.region_id, i32 3, i8** [[TMP17]], i8** [[TMP18]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP19]], i32 [[TMP21]])
|
|
// CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK9-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK9: omp_offload.failed:
|
|
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116(%struct.SS* @Gbla, %struct.SS* [[LA]], i64 [[TMP1]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK9: omp_offload.cont:
|
|
// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[COMP_CASTED2]] to i32*
|
|
// CHECK9-NEXT: store i32 [[TMP24]], i32* [[CONV3]], align 4
|
|
// CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[COMP_CASTED2]], align 8
|
|
// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.SS.0**
|
|
// CHECK9-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP27]], align 8
|
|
// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to %struct.SS.0**
|
|
// CHECK9-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP29]], align 8
|
|
// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
|
|
// CHECK9-NEXT: store i8* null, i8** [[TMP30]], align 8
|
|
// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1
|
|
// CHECK9-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to %struct.SS.0**
|
|
// CHECK9-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP32]], align 8
|
|
// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1
|
|
// CHECK9-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to %struct.SS.0**
|
|
// CHECK9-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP34]], align 8
|
|
// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1
|
|
// CHECK9-NEXT: store i8* null, i8** [[TMP35]], align 8
|
|
// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2
|
|
// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64*
|
|
// CHECK9-NEXT: store i64 [[TMP25]], i64* [[TMP37]], align 8
|
|
// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2
|
|
// CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64*
|
|
// CHECK9-NEXT: store i64 [[TMP25]], i64* [[TMP39]], align 8
|
|
// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 2
|
|
// CHECK9-NEXT: store i8* null, i8** [[TMP40]], align 8
|
|
// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[LB]], i32 0, i32 1
|
|
// CHECK9-NEXT: [[TMP43:%.*]] = load float, float* [[B7]], align 8
|
|
// CHECK9-NEXT: [[CONV8:%.*]] = fptosi float [[TMP43]] to i64
|
|
// CHECK9-NEXT: [[TMP44:%.*]] = trunc i64 [[CONV8]] to i32
|
|
// CHECK9-NEXT: [[TMP45:%.*]] = load i64, i64* getelementptr inbounds ([[STRUCT_SS_0]], %struct.SS.0* @Gblb, i32 0, i32 0), align 8
|
|
// CHECK9-NEXT: [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32
|
|
// CHECK9-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125.region_id, i32 3, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 [[TMP44]], i32 [[TMP46]])
|
|
// CHECK9-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0
|
|
// CHECK9-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
|
|
// CHECK9: omp_offload.failed9:
|
|
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125(%struct.SS.0* [[LB]], %struct.SS.0* @Gblb, i64 [[TMP25]]) #[[ATTR2]]
|
|
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT10]]
|
|
// CHECK9: omp_offload.cont10:
|
|
// CHECK9-NEXT: [[TMP49:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK9-NEXT: ret i32 [[TMP49]]
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116
|
|
// CHECK9-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK9-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK9-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK9-NEXT: store %struct.SS* [[GBLA]], %struct.SS** [[GBLA_ADDR]], align 8
|
|
// CHECK9-NEXT: store %struct.SS* [[LA]], %struct.SS** [[LA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[GBLA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.SS*, %struct.SS** [[LA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP2]], i32 0, i32 1
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load float, float* [[B]], align 4
|
|
// CHECK9-NEXT: [[CONV1:%.*]] = fptosi float [[TMP4]] to i64
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = trunc i64 [[CONV1]] to i32
|
|
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK9-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125
|
|
// CHECK9-SAME: (%struct.SS.0* nonnull align 8 dereferenceable(16) [[LB:%.*]], %struct.SS.0* nonnull align 8 dereferenceable(16) [[GBLB:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 8
|
|
// CHECK9-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 8
|
|
// CHECK9-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK9-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[LB_ADDR]], align 8
|
|
// CHECK9-NEXT: store %struct.SS.0* [[GBLB]], %struct.SS.0** [[GBLB_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.SS.0*, %struct.SS.0** [[LB_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.SS.0*, %struct.SS.0** [[GBLB_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS_0:%.*]], %struct.SS.0* [[TMP1]], i32 0, i32 1
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[B]], align 8
|
|
// CHECK9-NEXT: [[CONV1:%.*]] = fptosi float [[TMP3]] to i64
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = trunc i64 [[CONV1]] to i32
|
|
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[TMP2]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[A]], align 8
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
|
|
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 [[TMP6]])
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK9-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@_Z18teams_template_argv
|
|
// CHECK10-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[COMP:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
|
|
// CHECK10-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 8
|
|
// CHECK10-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK10-NEXT: [[COMP_CASTED2:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK10-NEXT: store i32 1, i32* [[COMP]], align 4
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_CASTED]] to i32*
|
|
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[COMP_CASTED]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS**
|
|
// CHECK10-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP3]], align 8
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to %struct.SS**
|
|
// CHECK10-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP5]], align 8
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK10-NEXT: store i8* null, i8** [[TMP6]], align 8
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to %struct.SS**
|
|
// CHECK10-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP8]], align 8
|
|
// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS**
|
|
// CHECK10-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP10]], align 8
|
|
// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8
|
|
// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8
|
|
// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
|
|
// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8
|
|
// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK10-NEXT: store i8* null, i8** [[TMP16]], align 8
|
|
// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SS]], %struct.SS* @Gbla, i32 0, i32 0), align 4
|
|
// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[LA]], i32 0, i32 1
|
|
// CHECK10-NEXT: [[TMP20:%.*]] = load float, float* [[B]], align 4
|
|
// CHECK10-NEXT: [[CONV1:%.*]] = fptosi float [[TMP20]] to i64
|
|
// CHECK10-NEXT: [[TMP21:%.*]] = trunc i64 [[CONV1]] to i32
|
|
// CHECK10-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116.region_id, i32 3, i8** [[TMP17]], i8** [[TMP18]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP19]], i32 [[TMP21]])
|
|
// CHECK10-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK10-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK10: omp_offload.failed:
|
|
// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116(%struct.SS* @Gbla, %struct.SS* [[LA]], i64 [[TMP1]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK10: omp_offload.cont:
|
|
// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[COMP_CASTED2]] to i32*
|
|
// CHECK10-NEXT: store i32 [[TMP24]], i32* [[CONV3]], align 4
|
|
// CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[COMP_CASTED2]], align 8
|
|
// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.SS.0**
|
|
// CHECK10-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP27]], align 8
|
|
// CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to %struct.SS.0**
|
|
// CHECK10-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP29]], align 8
|
|
// CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
|
|
// CHECK10-NEXT: store i8* null, i8** [[TMP30]], align 8
|
|
// CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1
|
|
// CHECK10-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to %struct.SS.0**
|
|
// CHECK10-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP32]], align 8
|
|
// CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1
|
|
// CHECK10-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to %struct.SS.0**
|
|
// CHECK10-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP34]], align 8
|
|
// CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1
|
|
// CHECK10-NEXT: store i8* null, i8** [[TMP35]], align 8
|
|
// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2
|
|
// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64*
|
|
// CHECK10-NEXT: store i64 [[TMP25]], i64* [[TMP37]], align 8
|
|
// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2
|
|
// CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64*
|
|
// CHECK10-NEXT: store i64 [[TMP25]], i64* [[TMP39]], align 8
|
|
// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 2
|
|
// CHECK10-NEXT: store i8* null, i8** [[TMP40]], align 8
|
|
// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[LB]], i32 0, i32 1
|
|
// CHECK10-NEXT: [[TMP43:%.*]] = load float, float* [[B7]], align 8
|
|
// CHECK10-NEXT: [[CONV8:%.*]] = fptosi float [[TMP43]] to i64
|
|
// CHECK10-NEXT: [[TMP44:%.*]] = trunc i64 [[CONV8]] to i32
|
|
// CHECK10-NEXT: [[TMP45:%.*]] = load i64, i64* getelementptr inbounds ([[STRUCT_SS_0]], %struct.SS.0* @Gblb, i32 0, i32 0), align 8
|
|
// CHECK10-NEXT: [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32
|
|
// CHECK10-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125.region_id, i32 3, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 [[TMP44]], i32 [[TMP46]])
|
|
// CHECK10-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0
|
|
// CHECK10-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
|
|
// CHECK10: omp_offload.failed9:
|
|
// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125(%struct.SS.0* [[LB]], %struct.SS.0* @Gblb, i64 [[TMP25]]) #[[ATTR2]]
|
|
// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT10]]
|
|
// CHECK10: omp_offload.cont10:
|
|
// CHECK10-NEXT: [[TMP49:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK10-NEXT: ret i32 [[TMP49]]
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116
|
|
// CHECK10-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK10-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK10-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK10-NEXT: store %struct.SS* [[GBLA]], %struct.SS** [[GBLA_ADDR]], align 8
|
|
// CHECK10-NEXT: store %struct.SS* [[LA]], %struct.SS** [[LA_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[GBLA_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.SS*, %struct.SS** [[LA_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP2]], i32 0, i32 1
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load float, float* [[B]], align 4
|
|
// CHECK10-NEXT: [[CONV1:%.*]] = fptosi float [[TMP4]] to i64
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = trunc i64 [[CONV1]] to i32
|
|
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK10-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125
|
|
// CHECK10-SAME: (%struct.SS.0* nonnull align 8 dereferenceable(16) [[LB:%.*]], %struct.SS.0* nonnull align 8 dereferenceable(16) [[GBLB:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 8
|
|
// CHECK10-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 8
|
|
// CHECK10-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK10-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[LB_ADDR]], align 8
|
|
// CHECK10-NEXT: store %struct.SS.0* [[GBLB]], %struct.SS.0** [[GBLB_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.SS.0*, %struct.SS.0** [[LB_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.SS.0*, %struct.SS.0** [[GBLB_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS_0:%.*]], %struct.SS.0* [[TMP1]], i32 0, i32 1
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load float, float* [[B]], align 8
|
|
// CHECK10-NEXT: [[CONV1:%.*]] = fptosi float [[TMP3]] to i64
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = trunc i64 [[CONV1]] to i32
|
|
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[TMP2]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[A]], align 8
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
|
|
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 [[TMP6]])
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK10-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK10-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@_Z18teams_template_argv
|
|
// CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[COMP:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
|
|
// CHECK11-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 4
|
|
// CHECK11-NEXT: [[COMP_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK11-NEXT: [[COMP_CASTED1:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK11-NEXT: store i32 1, i32* [[COMP]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[COMP_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS**
|
|
// CHECK11-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP3]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to %struct.SS**
|
|
// CHECK11-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP5]], align 4
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK11-NEXT: store i8* null, i8** [[TMP6]], align 4
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to %struct.SS**
|
|
// CHECK11-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP8]], align 4
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS**
|
|
// CHECK11-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP10]], align 4
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP13]], align 4
|
|
// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
|
|
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP15]], align 4
|
|
// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4
|
|
// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SS]], %struct.SS* @Gbla, i32 0, i32 0), align 4
|
|
// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[LA]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[TMP20:%.*]] = load float, float* [[B]], align 4
|
|
// CHECK11-NEXT: [[CONV:%.*]] = fptosi float [[TMP20]] to i64
|
|
// CHECK11-NEXT: [[TMP21:%.*]] = trunc i64 [[CONV]] to i32
|
|
// CHECK11-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116.region_id, i32 3, i8** [[TMP17]], i8** [[TMP18]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP19]], i32 [[TMP21]])
|
|
// CHECK11-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK11-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK11: omp_offload.failed:
|
|
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116(%struct.SS* @Gbla, %struct.SS* [[LA]], i32 [[TMP1]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK11: omp_offload.cont:
|
|
// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP24]], i32* [[COMP_CASTED1]], align 4
|
|
// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[COMP_CASTED1]], align 4
|
|
// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.SS.0**
|
|
// CHECK11-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP27]], align 4
|
|
// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to %struct.SS.0**
|
|
// CHECK11-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP29]], align 4
|
|
// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0
|
|
// CHECK11-NEXT: store i8* null, i8** [[TMP30]], align 4
|
|
// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to %struct.SS.0**
|
|
// CHECK11-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP32]], align 4
|
|
// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to %struct.SS.0**
|
|
// CHECK11-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP34]], align 4
|
|
// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1
|
|
// CHECK11-NEXT: store i8* null, i8** [[TMP35]], align 4
|
|
// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32*
|
|
// CHECK11-NEXT: store i32 [[TMP25]], i32* [[TMP37]], align 4
|
|
// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32*
|
|
// CHECK11-NEXT: store i32 [[TMP25]], i32* [[TMP39]], align 4
|
|
// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 2
|
|
// CHECK11-NEXT: store i8* null, i8** [[TMP40]], align 4
|
|
// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[LB]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[TMP43:%.*]] = load float, float* [[B5]], align 4
|
|
// CHECK11-NEXT: [[CONV6:%.*]] = fptosi float [[TMP43]] to i64
|
|
// CHECK11-NEXT: [[TMP44:%.*]] = trunc i64 [[CONV6]] to i32
|
|
// CHECK11-NEXT: [[TMP45:%.*]] = load i64, i64* getelementptr inbounds ([[STRUCT_SS_0]], %struct.SS.0* @Gblb, i32 0, i32 0), align 4
|
|
// CHECK11-NEXT: [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32
|
|
// CHECK11-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125.region_id, i32 3, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 [[TMP44]], i32 [[TMP46]])
|
|
// CHECK11-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0
|
|
// CHECK11-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
|
|
// CHECK11: omp_offload.failed7:
|
|
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125(%struct.SS.0* [[LB]], %struct.SS.0* @Gblb, i32 [[TMP25]]) #[[ATTR2]]
|
|
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT8]]
|
|
// CHECK11: omp_offload.cont8:
|
|
// CHECK11-NEXT: [[TMP49:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK11-NEXT: ret i32 [[TMP49]]
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116
|
|
// CHECK11-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK11-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK11-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK11-NEXT: store %struct.SS* [[GBLA]], %struct.SS** [[GBLA_ADDR]], align 4
|
|
// CHECK11-NEXT: store %struct.SS* [[LA]], %struct.SS** [[LA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[GBLA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.SS*, %struct.SS** [[LA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP2]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load float, float* [[B]], align 4
|
|
// CHECK11-NEXT: [[CONV:%.*]] = fptosi float [[TMP4]] to i64
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = trunc i64 [[CONV]] to i32
|
|
// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK11-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125
|
|
// CHECK11-SAME: (%struct.SS.0* nonnull align 4 dereferenceable(12) [[LB:%.*]], %struct.SS.0* nonnull align 4 dereferenceable(12) [[GBLB:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 4
|
|
// CHECK11-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 4
|
|
// CHECK11-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK11-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[LB_ADDR]], align 4
|
|
// CHECK11-NEXT: store %struct.SS.0* [[GBLB]], %struct.SS.0** [[GBLB_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.SS.0*, %struct.SS.0** [[LB_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load %struct.SS.0*, %struct.SS.0** [[GBLB_ADDR]], align 4
|
|
// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS_0:%.*]], %struct.SS.0* [[TMP1]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load float, float* [[B]], align 4
|
|
// CHECK11-NEXT: [[CONV:%.*]] = fptosi float [[TMP3]] to i64
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = trunc i64 [[CONV]] to i32
|
|
// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[TMP2]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[A]], align 4
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
|
|
// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 [[TMP6]])
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK11-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@_Z18teams_template_argv
|
|
// CHECK12-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[COMP:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
|
|
// CHECK12-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 4
|
|
// CHECK12-NEXT: [[COMP_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK12-NEXT: [[COMP_CASTED1:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK12-NEXT: store i32 1, i32* [[COMP]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[COMP_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS**
|
|
// CHECK12-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP3]], align 4
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to %struct.SS**
|
|
// CHECK12-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP5]], align 4
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK12-NEXT: store i8* null, i8** [[TMP6]], align 4
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to %struct.SS**
|
|
// CHECK12-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP8]], align 4
|
|
// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS**
|
|
// CHECK12-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP10]], align 4
|
|
// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4
|
|
// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP13]], align 4
|
|
// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
|
|
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP15]], align 4
|
|
// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4
|
|
// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SS]], %struct.SS* @Gbla, i32 0, i32 0), align 4
|
|
// CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[LA]], i32 0, i32 1
|
|
// CHECK12-NEXT: [[TMP20:%.*]] = load float, float* [[B]], align 4
|
|
// CHECK12-NEXT: [[CONV:%.*]] = fptosi float [[TMP20]] to i64
|
|
// CHECK12-NEXT: [[TMP21:%.*]] = trunc i64 [[CONV]] to i32
|
|
// CHECK12-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116.region_id, i32 3, i8** [[TMP17]], i8** [[TMP18]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP19]], i32 [[TMP21]])
|
|
// CHECK12-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK12-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK12: omp_offload.failed:
|
|
// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116(%struct.SS* @Gbla, %struct.SS* [[LA]], i32 [[TMP1]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK12: omp_offload.cont:
|
|
// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP24]], i32* [[COMP_CASTED1]], align 4
|
|
// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[COMP_CASTED1]], align 4
|
|
// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.SS.0**
|
|
// CHECK12-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP27]], align 4
|
|
// CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to %struct.SS.0**
|
|
// CHECK12-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP29]], align 4
|
|
// CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0
|
|
// CHECK12-NEXT: store i8* null, i8** [[TMP30]], align 4
|
|
// CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1
|
|
// CHECK12-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to %struct.SS.0**
|
|
// CHECK12-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP32]], align 4
|
|
// CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1
|
|
// CHECK12-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to %struct.SS.0**
|
|
// CHECK12-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP34]], align 4
|
|
// CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1
|
|
// CHECK12-NEXT: store i8* null, i8** [[TMP35]], align 4
|
|
// CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2
|
|
// CHECK12-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32*
|
|
// CHECK12-NEXT: store i32 [[TMP25]], i32* [[TMP37]], align 4
|
|
// CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 2
|
|
// CHECK12-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32*
|
|
// CHECK12-NEXT: store i32 [[TMP25]], i32* [[TMP39]], align 4
|
|
// CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 2
|
|
// CHECK12-NEXT: store i8* null, i8** [[TMP40]], align 4
|
|
// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[LB]], i32 0, i32 1
|
|
// CHECK12-NEXT: [[TMP43:%.*]] = load float, float* [[B5]], align 4
|
|
// CHECK12-NEXT: [[CONV6:%.*]] = fptosi float [[TMP43]] to i64
|
|
// CHECK12-NEXT: [[TMP44:%.*]] = trunc i64 [[CONV6]] to i32
|
|
// CHECK12-NEXT: [[TMP45:%.*]] = load i64, i64* getelementptr inbounds ([[STRUCT_SS_0]], %struct.SS.0* @Gblb, i32 0, i32 0), align 4
|
|
// CHECK12-NEXT: [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32
|
|
// CHECK12-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125.region_id, i32 3, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 [[TMP44]], i32 [[TMP46]])
|
|
// CHECK12-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0
|
|
// CHECK12-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
|
|
// CHECK12: omp_offload.failed7:
|
|
// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125(%struct.SS.0* [[LB]], %struct.SS.0* @Gblb, i32 [[TMP25]]) #[[ATTR2]]
|
|
// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT8]]
|
|
// CHECK12: omp_offload.cont8:
|
|
// CHECK12-NEXT: [[TMP49:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK12-NEXT: ret i32 [[TMP49]]
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116
|
|
// CHECK12-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK12-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK12-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK12-NEXT: store %struct.SS* [[GBLA]], %struct.SS** [[GBLA_ADDR]], align 4
|
|
// CHECK12-NEXT: store %struct.SS* [[LA]], %struct.SS** [[LA_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[GBLA_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.SS*, %struct.SS** [[LA_ADDR]], align 4
|
|
// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP2]], i32 0, i32 1
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load float, float* [[B]], align 4
|
|
// CHECK12-NEXT: [[CONV:%.*]] = fptosi float [[TMP4]] to i64
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = trunc i64 [[CONV]] to i32
|
|
// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK12-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125
|
|
// CHECK12-SAME: (%struct.SS.0* nonnull align 4 dereferenceable(12) [[LB:%.*]], %struct.SS.0* nonnull align 4 dereferenceable(12) [[GBLB:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 4
|
|
// CHECK12-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 4
|
|
// CHECK12-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK12-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[LB_ADDR]], align 4
|
|
// CHECK12-NEXT: store %struct.SS.0* [[GBLB]], %struct.SS.0** [[GBLB_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.SS.0*, %struct.SS.0** [[LB_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load %struct.SS.0*, %struct.SS.0** [[GBLB_ADDR]], align 4
|
|
// CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS_0:%.*]], %struct.SS.0* [[TMP1]], i32 0, i32 1
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load float, float* [[B]], align 4
|
|
// CHECK12-NEXT: [[CONV:%.*]] = fptosi float [[TMP3]] to i64
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = trunc i64 [[CONV]] to i32
|
|
// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[TMP2]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i64, i64* [[A]], align 4
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
|
|
// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 [[TMP6]])
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK12-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK12-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_Z21teams_template_structv
|
|
// CHECK17-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
|
|
// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(8) [[V]])
|
|
// CHECK17-NEXT: ret i32 [[CALL]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
|
|
// CHECK17-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK17-NEXT: [[COMP:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK17-NEXT: [[COMP_CASTED3:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: store i32 1, i32* [[COMP]], align 4
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[COMP_CASTED]], align 8
|
|
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS**
|
|
// CHECK17-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP3]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32**
|
|
// CHECK17-NEXT: store i32* [[A]], i32** [[TMP5]], align 8
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP6]], align 8
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[A2]], align 4
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161.region_id, i32 2, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP14]], i32 123)
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK17: omp_offload.failed:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161(%struct.SS* [[THIS1]], i64 [[TMP1]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK17: omp_offload.cont:
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[COMP_CASTED3]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP17]], i32* [[CONV4]], align 4
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = load i64, i64* [[COMP_CASTED3]], align 8
|
|
// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.SS**
|
|
// CHECK17-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP20]], align 8
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
|
|
// CHECK17-NEXT: store float* [[B]], float** [[TMP22]], align 8
|
|
// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8
|
|
// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP18]], i64* [[TMP25]], align 8
|
|
// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP18]], i64* [[TMP27]], align 8
|
|
// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP28]], align 8
|
|
// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[B8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP31:%.*]] = load float, float* [[B8]], align 4
|
|
// CHECK17-NEXT: [[CONV9:%.*]] = fptosi float [[TMP31]] to i32
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 123
|
|
// CHECK17-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169.region_id, i32 2, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 456, i32 [[ADD]])
|
|
// CHECK17-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]]
|
|
// CHECK17: omp_offload.failed10:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169(%struct.SS* [[THIS1]], i64 [[TMP18]]) #[[ATTR2]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT11]]
|
|
// CHECK17: omp_offload.cont11:
|
|
// CHECK17-NEXT: [[TMP34:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK17-NEXT: ret i32 [[TMP34]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161
|
|
// CHECK17-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK17-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 123)
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK17-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK17-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169
|
|
// CHECK17-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK17-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load float, float* [[B]], align 4
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = fptosi float [[TMP2]] to i32
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 123
|
|
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 456, i32 [[ADD]])
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK17-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK17-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK17-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@_Z21teams_template_structv
|
|
// CHECK18-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
|
|
// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(8) [[V]])
|
|
// CHECK18-NEXT: ret i32 [[CALL]]
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
|
|
// CHECK18-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK18-NEXT: [[COMP:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK18-NEXT: [[COMP_CASTED3:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: store i32 1, i32* [[COMP]], align 4
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[COMP_CASTED]], align 8
|
|
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS**
|
|
// CHECK18-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP3]], align 8
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32**
|
|
// CHECK18-NEXT: store i32* [[A]], i32** [[TMP5]], align 8
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP6]], align 8
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP11]], align 8
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[A2]], align 4
|
|
// CHECK18-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161.region_id, i32 2, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP14]], i32 123)
|
|
// CHECK18-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK18: omp_offload.failed:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161(%struct.SS* [[THIS1]], i64 [[TMP1]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK18: omp_offload.cont:
|
|
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[COMP_CASTED3]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP17]], i32* [[CONV4]], align 4
|
|
// CHECK18-NEXT: [[TMP18:%.*]] = load i64, i64* [[COMP_CASTED3]], align 8
|
|
// CHECK18-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.SS**
|
|
// CHECK18-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP20]], align 8
|
|
// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
|
|
// CHECK18-NEXT: store float* [[B]], float** [[TMP22]], align 8
|
|
// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8
|
|
// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP18]], i64* [[TMP25]], align 8
|
|
// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP18]], i64* [[TMP27]], align 8
|
|
// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP28]], align 8
|
|
// CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[B8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP31:%.*]] = load float, float* [[B8]], align 4
|
|
// CHECK18-NEXT: [[CONV9:%.*]] = fptosi float [[TMP31]] to i32
|
|
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 123
|
|
// CHECK18-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169.region_id, i32 2, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 456, i32 [[ADD]])
|
|
// CHECK18-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]]
|
|
// CHECK18: omp_offload.failed10:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169(%struct.SS* [[THIS1]], i64 [[TMP18]]) #[[ATTR2]]
|
|
// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT11]]
|
|
// CHECK18: omp_offload.cont11:
|
|
// CHECK18-NEXT: [[TMP34:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK18-NEXT: ret i32 [[TMP34]]
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161
|
|
// CHECK18-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK18-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 123)
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK18-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169
|
|
// CHECK18-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK18-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load float, float* [[B]], align 4
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = fptosi float [[TMP2]] to i32
|
|
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 123
|
|
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 456, i32 [[ADD]])
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK18-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK18-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_Z21teams_template_structv
|
|
// CHECK19-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
|
|
// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(8) [[V]])
|
|
// CHECK19-NEXT: ret i32 [[CALL]]
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
|
|
// CHECK19-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK19-NEXT: [[COMP:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[COMP_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK19-NEXT: [[COMP_CASTED3:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 1, i32* [[COMP]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[COMP_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP_CASTED]], align 4
|
|
// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS**
|
|
// CHECK19-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP3]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32**
|
|
// CHECK19-NEXT: store i32* [[A]], i32** [[TMP5]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP6]], align 4
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[A2]], align 4
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161.region_id, i32 2, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP14]], i32 123)
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK19: omp_offload.failed:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161(%struct.SS* [[THIS1]], i32 [[TMP1]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK19: omp_offload.cont:
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP17]], i32* [[COMP_CASTED3]], align 4
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[COMP_CASTED3]], align 4
|
|
// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.SS**
|
|
// CHECK19-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP20]], align 4
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
|
|
// CHECK19-NEXT: store float* [[B]], float** [[TMP22]], align 4
|
|
// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP23]], align 4
|
|
// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP18]], i32* [[TMP25]], align 4
|
|
// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP18]], i32* [[TMP27]], align 4
|
|
// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP28]], align 4
|
|
// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP31:%.*]] = load float, float* [[B7]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = fptosi float [[TMP31]] to i32
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 123
|
|
// CHECK19-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169.region_id, i32 2, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 456, i32 [[ADD]])
|
|
// CHECK19-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]]
|
|
// CHECK19: omp_offload.failed8:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169(%struct.SS* [[THIS1]], i32 [[TMP18]]) #[[ATTR2]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT9]]
|
|
// CHECK19: omp_offload.cont9:
|
|
// CHECK19-NEXT: [[TMP34:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK19-NEXT: ret i32 [[TMP34]]
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161
|
|
// CHECK19-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK19-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 123)
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK19-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK19-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169
|
|
// CHECK19-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK19-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load float, float* [[B]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = fptosi float [[TMP2]] to i32
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 123
|
|
// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 456, i32 [[ADD]])
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK19-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK19-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK19-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@_Z21teams_template_structv
|
|
// CHECK20-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
|
|
// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(8) [[V]])
|
|
// CHECK20-NEXT: ret i32 [[CALL]]
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
|
|
// CHECK20-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK20-NEXT: [[COMP:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[COMP_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK20-NEXT: [[COMP_CASTED3:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 1, i32* [[COMP]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[COMP_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP_CASTED]], align 4
|
|
// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS**
|
|
// CHECK20-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP3]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32**
|
|
// CHECK20-NEXT: store i32* [[A]], i32** [[TMP5]], align 4
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP6]], align 4
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[A2]], align 4
|
|
// CHECK20-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161.region_id, i32 2, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP14]], i32 123)
|
|
// CHECK20-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK20: omp_offload.failed:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161(%struct.SS* [[THIS1]], i32 [[TMP1]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK20: omp_offload.cont:
|
|
// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP17]], i32* [[COMP_CASTED3]], align 4
|
|
// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[COMP_CASTED3]], align 4
|
|
// CHECK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.SS**
|
|
// CHECK20-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP20]], align 4
|
|
// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
|
|
// CHECK20-NEXT: store float* [[B]], float** [[TMP22]], align 4
|
|
// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP23]], align 4
|
|
// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP18]], i32* [[TMP25]], align 4
|
|
// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP18]], i32* [[TMP27]], align 4
|
|
// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP28]], align 4
|
|
// CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP31:%.*]] = load float, float* [[B7]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = fptosi float [[TMP31]] to i32
|
|
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 123
|
|
// CHECK20-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169.region_id, i32 2, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 456, i32 [[ADD]])
|
|
// CHECK20-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]]
|
|
// CHECK20: omp_offload.failed8:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169(%struct.SS* [[THIS1]], i32 [[TMP18]]) #[[ATTR2]]
|
|
// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT9]]
|
|
// CHECK20: omp_offload.cont9:
|
|
// CHECK20-NEXT: [[TMP34:%.*]] = load i32, i32* [[COMP]], align 4
|
|
// CHECK20-NEXT: ret i32 [[TMP34]]
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161
|
|
// CHECK20-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK20-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 123)
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK20-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK20-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169
|
|
// CHECK20-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK20-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load float, float* [[B]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = fptosi float [[TMP2]] to i32
|
|
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 123
|
|
// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 456, i32 [[ADD]])
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK20-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
|
// CHECK20-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK20-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216
|
|
// CHECK25-SAME: (i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
|
|
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]])
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8
|
|
// CHECK25-NEXT: store i32 0, i32* [[TMP0]], align 4
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209
|
|
// CHECK25-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8
|
|
// CHECK25-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8
|
|
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]])
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 8
|
|
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8
|
|
// CHECK25-NEXT: store i8** null, i8*** [[TMP0]], align 8
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216
|
|
// CHECK26-SAME: (i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
|
|
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]])
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8
|
|
// CHECK26-NEXT: store i32 0, i32* [[TMP0]], align 4
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209
|
|
// CHECK26-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8
|
|
// CHECK26-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8
|
|
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]])
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 8
|
|
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8
|
|
// CHECK26-NEXT: store i8** null, i8*** [[TMP0]], align 8
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216
|
|
// CHECK27-SAME: (i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]])
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 0, i32* [[TMP0]], align 4
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209
|
|
// CHECK27-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4
|
|
// CHECK27-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4
|
|
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]])
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 4
|
|
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 4
|
|
// CHECK27-NEXT: store i8** null, i8*** [[TMP0]], align 4
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216
|
|
// CHECK28-SAME: (i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]])
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 0, i32* [[TMP0]], align 4
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209
|
|
// CHECK28-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4
|
|
// CHECK28-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4
|
|
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]])
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 4
|
|
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 4
|
|
// CHECK28-NEXT: store i8** null, i8*** [[TMP0]], align 4
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265
|
|
// CHECK33-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK33-NEXT: entry:
|
|
// CHECK33-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK33-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK33-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
|
|
// CHECK33-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK33-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK33-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
|
|
// CHECK33-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK33-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK33-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
|
|
// CHECK33-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK33-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
|
|
// CHECK33-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]])
|
|
// CHECK33-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK33-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK33-NEXT: entry:
|
|
// CHECK33-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK33-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK33-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK33-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK33-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8
|
|
// CHECK33-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8
|
|
// CHECK33-NEXT: store i32 0, i32* [[TMP0]], align 4
|
|
// CHECK33-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254
|
|
// CHECK33-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK33-NEXT: entry:
|
|
// CHECK33-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK33-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8
|
|
// CHECK33-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK33-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK33-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK33-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8
|
|
// CHECK33-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK33-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK33-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK33-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
|
|
// CHECK33-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]])
|
|
// CHECK33-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK33-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK33-NEXT: entry:
|
|
// CHECK33-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK33-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 8
|
|
// CHECK33-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK33-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK33-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 8
|
|
// CHECK33-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8
|
|
// CHECK33-NEXT: store i8** null, i8*** [[TMP0]], align 8
|
|
// CHECK33-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK34-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265
|
|
// CHECK34-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK34-NEXT: entry:
|
|
// CHECK34-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK34-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK34-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
|
|
// CHECK34-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK34-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK34-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
|
|
// CHECK34-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK34-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK34-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
|
|
// CHECK34-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK34-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
|
|
// CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]])
|
|
// CHECK34-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK34-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK34-NEXT: entry:
|
|
// CHECK34-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK34-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK34-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK34-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK34-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8
|
|
// CHECK34-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8
|
|
// CHECK34-NEXT: store i32 0, i32* [[TMP0]], align 4
|
|
// CHECK34-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK34-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254
|
|
// CHECK34-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK34-NEXT: entry:
|
|
// CHECK34-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK34-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8
|
|
// CHECK34-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK34-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK34-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK34-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8
|
|
// CHECK34-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK34-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK34-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK34-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
|
|
// CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]])
|
|
// CHECK34-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK34-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK34-NEXT: entry:
|
|
// CHECK34-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK34-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 8
|
|
// CHECK34-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK34-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK34-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 8
|
|
// CHECK34-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8
|
|
// CHECK34-NEXT: store i8** null, i8*** [[TMP0]], align 8
|
|
// CHECK34-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265
|
|
// CHECK35-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK35-NEXT: entry:
|
|
// CHECK35-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK35-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK35-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
|
|
// CHECK35-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK35-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK35-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK35-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK35-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK35-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
|
|
// CHECK35-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]])
|
|
// CHECK35-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK35-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK35-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK35-NEXT: entry:
|
|
// CHECK35-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK35-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK35-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK35-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK35-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4
|
|
// CHECK35-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4
|
|
// CHECK35-NEXT: store i32 0, i32* [[TMP0]], align 4
|
|
// CHECK35-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254
|
|
// CHECK35-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK35-NEXT: entry:
|
|
// CHECK35-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK35-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4
|
|
// CHECK35-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK35-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK35-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK35-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4
|
|
// CHECK35-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK35-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK35-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
|
|
// CHECK35-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]])
|
|
// CHECK35-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK35-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK35-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK35-NEXT: entry:
|
|
// CHECK35-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK35-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 4
|
|
// CHECK35-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK35-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK35-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 4
|
|
// CHECK35-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 4
|
|
// CHECK35-NEXT: store i8** null, i8*** [[TMP0]], align 4
|
|
// CHECK35-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK36-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265
|
|
// CHECK36-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK36-NEXT: entry:
|
|
// CHECK36-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK36-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK36-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK36-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
|
|
// CHECK36-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK36-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK36-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK36-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK36-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK36-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
|
|
// CHECK36-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]])
|
|
// CHECK36-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK36-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK36-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK36-NEXT: entry:
|
|
// CHECK36-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK36-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK36-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK36-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK36-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK36-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4
|
|
// CHECK36-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4
|
|
// CHECK36-NEXT: store i32 0, i32* [[TMP0]], align 4
|
|
// CHECK36-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK36-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254
|
|
// CHECK36-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK36-NEXT: entry:
|
|
// CHECK36-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK36-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK36-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4
|
|
// CHECK36-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK36-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK36-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK36-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4
|
|
// CHECK36-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK36-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK36-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
|
|
// CHECK36-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]])
|
|
// CHECK36-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK36-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK36-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] {
|
|
// CHECK36-NEXT: entry:
|
|
// CHECK36-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK36-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK36-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 4
|
|
// CHECK36-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK36-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK36-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 4
|
|
// CHECK36-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 4
|
|
// CHECK36-NEXT: store i8** null, i8*** [[TMP0]], align 4
|
|
// CHECK36-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK41-LABEL: define {{[^@]+}}@_Z3foov
|
|
// CHECK41-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK41-NEXT: entry:
|
|
// CHECK41-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK41-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK41-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK41-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK41-NEXT: entry:
|
|
// CHECK41-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK41-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK41-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK41-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK41-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK42-LABEL: define {{[^@]+}}@_Z3foov
|
|
// CHECK42-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK42-NEXT: entry:
|
|
// CHECK42-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK42-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK42-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK42-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK42-NEXT: entry:
|
|
// CHECK42-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK42-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK42-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK42-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK42-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK43-LABEL: define {{[^@]+}}@_Z3foov
|
|
// CHECK43-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK43-NEXT: entry:
|
|
// CHECK43-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK43-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK43-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK43-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK43-NEXT: entry:
|
|
// CHECK43-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK43-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK43-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK43-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK43-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK44-LABEL: define {{[^@]+}}@_Z3foov
|
|
// CHECK44-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK44-NEXT: entry:
|
|
// CHECK44-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK44-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK44-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK44-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK44-NEXT: entry:
|
|
// CHECK44-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK44-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK44-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK44-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK44-NEXT: ret void
|
|
//
|
|
//
|