forked from OSchip/llvm-project
1058 lines
37 KiB
C++
1058 lines
37 KiB
C++
//===- DFAPacketizerEmitter.cpp - Packetization DFA for a VLIW machine ----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class parses the Schedule.td file and produces an API that can be used
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// to reason about whether an instruction can be added to a packet on a VLIW
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// architecture. The class internally generates a deterministic finite
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// automaton (DFA) that models all possible mappings of machine instructions
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// to functional units as instructions are added to a packet.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "dfa-emitter"
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#include "CodeGenTarget.h"
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <cstdint>
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#include <map>
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#include <set>
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#include <string>
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#include <unordered_map>
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#include <vector>
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using namespace llvm;
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// --------------------------------------------------------------------
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// Definitions shared between DFAPacketizer.cpp and DFAPacketizerEmitter.cpp
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// DFA_MAX_RESTERMS * DFA_MAX_RESOURCES must fit within sizeof DFAInput.
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// This is verified in DFAPacketizer.cpp:DFAPacketizer::DFAPacketizer.
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//
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// e.g. terms x resource bit combinations that fit in uint32_t:
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// 4 terms x 8 bits = 32 bits
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// 3 terms x 10 bits = 30 bits
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// 2 terms x 16 bits = 32 bits
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//
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// e.g. terms x resource bit combinations that fit in uint64_t:
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// 8 terms x 8 bits = 64 bits
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// 7 terms x 9 bits = 63 bits
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// 6 terms x 10 bits = 60 bits
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// 5 terms x 12 bits = 60 bits
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// 4 terms x 16 bits = 64 bits <--- current
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// 3 terms x 21 bits = 63 bits
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// 2 terms x 32 bits = 64 bits
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//
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#define DFA_MAX_RESTERMS 4 // The max # of AND'ed resource terms.
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#define DFA_MAX_RESOURCES 16 // The max # of resource bits in one term.
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typedef uint64_t DFAInput;
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typedef int64_t DFAStateInput;
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#define DFA_TBLTYPE "int64_t" // For generating DFAStateInputTable.
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namespace {
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DFAInput addDFAFuncUnits(DFAInput Inp, unsigned FuncUnits) {
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return (Inp << DFA_MAX_RESOURCES) | FuncUnits;
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}
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/// Return the DFAInput for an instruction class input vector.
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/// This function is used in both DFAPacketizer.cpp and in
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/// DFAPacketizerEmitter.cpp.
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DFAInput getDFAInsnInput(const std::vector<unsigned> &InsnClass) {
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DFAInput InsnInput = 0;
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assert((InsnClass.size() <= DFA_MAX_RESTERMS) &&
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"Exceeded maximum number of DFA terms");
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for (auto U : InsnClass)
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InsnInput = addDFAFuncUnits(InsnInput, U);
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return InsnInput;
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}
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} // end anonymous namespace
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// --------------------------------------------------------------------
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#ifndef NDEBUG
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// To enable debugging, run llvm-tblgen with: "-debug-only dfa-emitter".
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//
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// dbgsInsnClass - When debugging, print instruction class stages.
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//
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void dbgsInsnClass(const std::vector<unsigned> &InsnClass);
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//
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// dbgsStateInfo - When debugging, print the set of state info.
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//
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void dbgsStateInfo(const std::set<unsigned> &stateInfo);
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//
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// dbgsIndent - When debugging, indent by the specified amount.
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//
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void dbgsIndent(unsigned indent);
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#endif
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//
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// class DFAPacketizerEmitter: class that generates and prints out the DFA
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// for resource tracking.
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//
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namespace {
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class DFAPacketizerEmitter {
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private:
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std::string TargetName;
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//
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// allInsnClasses is the set of all possible resources consumed by an
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// InstrStage.
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//
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std::vector<std::vector<unsigned>> allInsnClasses;
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RecordKeeper &Records;
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public:
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DFAPacketizerEmitter(RecordKeeper &R);
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//
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// collectAllFuncUnits - Construct a map of function unit names to bits.
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//
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int collectAllFuncUnits(std::vector<Record*> &ProcItinList,
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std::map<std::string, unsigned> &FUNameToBitsMap,
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int &maxResources,
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raw_ostream &OS);
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//
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// collectAllComboFuncs - Construct a map from a combo function unit bit to
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// the bits of all included functional units.
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//
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int collectAllComboFuncs(std::vector<Record*> &ComboFuncList,
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std::map<std::string, unsigned> &FUNameToBitsMap,
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std::map<unsigned, unsigned> &ComboBitToBitsMap,
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raw_ostream &OS);
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//
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// collectOneInsnClass - Populate allInsnClasses with one instruction class.
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//
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int collectOneInsnClass(const std::string &ProcName,
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std::vector<Record*> &ProcItinList,
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std::map<std::string, unsigned> &FUNameToBitsMap,
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Record *ItinData,
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raw_ostream &OS);
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//
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// collectAllInsnClasses - Populate allInsnClasses which is a set of units
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// used in each stage.
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//
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int collectAllInsnClasses(const std::string &ProcName,
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std::vector<Record*> &ProcItinList,
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std::map<std::string, unsigned> &FUNameToBitsMap,
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std::vector<Record*> &ItinDataList,
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int &maxStages,
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raw_ostream &OS);
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// Emit code for a subset of itineraries.
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void emitForItineraries(raw_ostream &OS,
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std::vector<Record *> &ProcItinList,
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std::string DFAName);
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void run(raw_ostream &OS);
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};
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//
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// State represents the usage of machine resources if the packet contains
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// a set of instruction classes.
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//
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// Specifically, currentState is a set of bit-masks.
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// The nth bit in a bit-mask indicates whether the nth resource is being used
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// by this state. The set of bit-masks in a state represent the different
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// possible outcomes of transitioning to this state.
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// For example: consider a two resource architecture: resource L and resource M
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// with three instruction classes: L, M, and L_or_M.
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// From the initial state (currentState = 0x00), if we add instruction class
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// L_or_M we will transition to a state with currentState = [0x01, 0x10]. This
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// represents the possible resource states that can result from adding a L_or_M
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// instruction
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//
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// Another way of thinking about this transition is we are mapping a NDFA with
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// two states [0x01] and [0x10] into a DFA with a single state [0x01, 0x10].
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//
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// A State instance also contains a collection of transitions from that state:
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// a map from inputs to new states.
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//
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class State {
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public:
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static int currentStateNum;
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// stateNum is the only member used for equality/ordering, all other members
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// can be mutated even in const State objects.
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const int stateNum;
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mutable bool isInitial;
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mutable std::set<unsigned> stateInfo;
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struct TransitionInfo {
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// Maps from a resource bitmask in this state to the equivalent resource
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// bitmap in the transitioned-to state. This is a 1-to-N mapping.
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std::vector<std::pair<unsigned, unsigned>> ResourceTransitions;
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const State *S;
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};
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using TransitionMap = std::map<std::vector<unsigned>, TransitionInfo>;
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mutable TransitionMap Transitions;
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State();
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bool operator<(const State &s) const {
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return stateNum < s.stateNum;
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}
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//
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// canMaybeAddInsnClass - Quickly verifies if an instruction of type InsnClass
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// may be a valid transition from this state i.e., can an instruction of type
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// InsnClass be added to the packet represented by this state.
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//
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// Note that for multiple stages, this quick check does not take into account
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// any possible resource competition between the stages themselves. That is
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// enforced in AddInsnClassStages which checks the cross product of all
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// stages for resource availability (which is a more involved check).
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//
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bool canMaybeAddInsnClass(std::vector<unsigned> &InsnClass,
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std::map<unsigned, unsigned> &ComboBitToBitsMap) const;
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//
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// AddInsnClass - Return all combinations of resource reservation
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// which are possible from this state (PossibleStates).
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//
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// PossibleStates is the set of valid resource states that ensue from valid
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// transitions.
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//
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// TransitionInfo maps from a resource bitmask B in this state to a resource
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// bitmask B' in PossibleStates. This is a one-to-many (or none) mapping.
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//
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void AddInsnClass(
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std::vector<unsigned> &InsnClass,
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std::map<unsigned, unsigned> &ComboBitToBitsMap,
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std::set<unsigned> &PossibleStates,
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std::vector<std::pair<unsigned, unsigned>> &TransitionInfo) const;
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//
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// AddInsnClassStages - Return all combinations of resource reservation
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// resulting from the cross product of all stages for this InsnClass
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// which are possible from this state (PossibleStates).
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//
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void AddInsnClassStages(std::vector<unsigned> &InsnClass,
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std::map<unsigned, unsigned> &ComboBitToBitsMap,
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unsigned chkstage, unsigned numstages,
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unsigned prevState, unsigned origState,
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DenseSet<unsigned> &VisitedResourceStates) const;
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//
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// addTransition - Add a transition from this state given the input InsnClass.
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//
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void addTransition(
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std::vector<unsigned> InsnClass, const State *To,
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const std::vector<std::pair<unsigned, unsigned>> &TransitionInfo) const;
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//
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// hasTransition - Returns true if there is a transition from this state
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// given the input InsnClass
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//
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bool hasTransition(std::vector<unsigned> InsnClass) const;
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};
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//
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// class DFA: deterministic finite automaton for processor resource tracking.
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//
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class DFA {
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public:
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DFA() = default;
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// Set of states. Need to keep this sorted to emit the transition table.
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typedef std::set<State> StateSet;
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StateSet states;
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State *currentState = nullptr;
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//
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// Modify the DFA.
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//
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const State &newState();
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//
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// writeTable: Print out a table representing the DFA.
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//
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void writeTableAndAPI(raw_ostream &OS, const std::string &ClassName,
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int numInsnClasses = 0,
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int maxResources = 0, int numCombos = 0, int maxStages = 0);
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};
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} // end anonymous namespace
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#ifndef NDEBUG
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// To enable debugging, run llvm-tblgen with: "-debug-only dfa-emitter".
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//
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// dbgsInsnClass - When debugging, print instruction class stages.
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//
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void dbgsInsnClass(const std::vector<unsigned> &InsnClass) {
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LLVM_DEBUG(dbgs() << "InsnClass: ");
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for (unsigned i = 0; i < InsnClass.size(); ++i) {
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if (i > 0) {
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LLVM_DEBUG(dbgs() << ", ");
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}
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LLVM_DEBUG(dbgs() << "0x" << Twine::utohexstr(InsnClass[i]));
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}
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DFAInput InsnInput = getDFAInsnInput(InsnClass);
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LLVM_DEBUG(dbgs() << " (input: 0x" << Twine::utohexstr(InsnInput) << ")");
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}
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//
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// dbgsStateInfo - When debugging, print the set of state info.
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//
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void dbgsStateInfo(const std::set<unsigned> &stateInfo) {
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LLVM_DEBUG(dbgs() << "StateInfo: ");
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unsigned i = 0;
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for (std::set<unsigned>::iterator SI = stateInfo.begin();
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SI != stateInfo.end(); ++SI, ++i) {
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unsigned thisState = *SI;
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if (i > 0) {
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LLVM_DEBUG(dbgs() << ", ");
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}
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LLVM_DEBUG(dbgs() << "0x" << Twine::utohexstr(thisState));
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}
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}
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//
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// dbgsIndent - When debugging, indent by the specified amount.
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//
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void dbgsIndent(unsigned indent) {
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for (unsigned i = 0; i < indent; ++i) {
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LLVM_DEBUG(dbgs() << " ");
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}
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}
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#endif // NDEBUG
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//
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// Constructors and destructors for State and DFA
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//
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State::State() :
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stateNum(currentStateNum++), isInitial(false) {}
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//
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// addTransition - Add a transition from this state given the input InsnClass
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//
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void State::addTransition(
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std::vector<unsigned> InsnClass, const State *To,
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const std::vector<std::pair<unsigned, unsigned>> &TransitionInfo) const {
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assert(!Transitions.count(InsnClass) &&
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"Cannot have multiple transitions for the same input");
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Transitions[InsnClass] = {TransitionInfo, To};
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}
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//
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// hasTransition - Returns true if there is a transition from this state
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// given the input InsnClass
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//
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bool State::hasTransition(std::vector<unsigned> InsnClass) const {
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return Transitions.count(InsnClass) > 0;
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}
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//
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// AddInsnClass - Return all combinations of resource reservation
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// which are possible from this state (PossibleStates).
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//
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// PossibleStates is the set of valid resource states that ensue from valid
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// transitions.
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//
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void State::AddInsnClass(
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std::vector<unsigned> &InsnClass,
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std::map<unsigned, unsigned> &ComboBitToBitsMap,
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std::set<unsigned> &PossibleStates,
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std::vector<std::pair<unsigned, unsigned>> &TransitionInfo) const {
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//
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// Iterate over all resource states in currentState.
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//
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unsigned numstages = InsnClass.size();
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assert((numstages > 0) && "InsnClass has no stages");
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for (std::set<unsigned>::iterator SI = stateInfo.begin();
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SI != stateInfo.end(); ++SI) {
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unsigned ThisState = *SI;
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DenseSet<unsigned> VisitedResourceStates;
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LLVM_DEBUG(dbgs() << " thisState: 0x" << Twine::utohexstr(ThisState)
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<< "\n");
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AddInsnClassStages(InsnClass, ComboBitToBitsMap, numstages - 1, numstages,
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ThisState, ThisState, VisitedResourceStates);
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for (unsigned NewState : VisitedResourceStates) {
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PossibleStates.insert(NewState);
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TransitionInfo.emplace_back(ThisState, NewState);
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}
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}
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}
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void State::AddInsnClassStages(
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std::vector<unsigned> &InsnClass,
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std::map<unsigned, unsigned> &ComboBitToBitsMap, unsigned chkstage,
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unsigned numstages, unsigned prevState, unsigned origState,
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DenseSet<unsigned> &VisitedResourceStates) const {
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assert((chkstage < numstages) && "AddInsnClassStages: stage out of range");
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unsigned thisStage = InsnClass[chkstage];
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LLVM_DEBUG({
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dbgsIndent((1 + numstages - chkstage) << 1);
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dbgs() << "AddInsnClassStages " << chkstage << " (0x"
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<< Twine::utohexstr(thisStage) << ") from ";
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dbgsInsnClass(InsnClass);
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dbgs() << "\n";
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});
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//
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// Iterate over all possible resources used in thisStage.
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// For ex: for thisStage = 0x11, all resources = {0x01, 0x10}.
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//
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for (unsigned int j = 0; j < DFA_MAX_RESOURCES; ++j) {
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unsigned resourceMask = (0x1 << j);
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if (resourceMask & thisStage) {
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unsigned combo = ComboBitToBitsMap[resourceMask];
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if (combo && ((~prevState & combo) != combo)) {
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LLVM_DEBUG(dbgs() << "\tSkipped Add 0x" << Twine::utohexstr(prevState)
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<< " - combo op 0x" << Twine::utohexstr(resourceMask)
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<< " (0x" << Twine::utohexstr(combo)
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<< ") cannot be scheduled\n");
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continue;
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}
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//
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// For each possible resource used in thisStage, generate the
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// resource state if that resource was used.
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//
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unsigned ResultingResourceState = prevState | resourceMask | combo;
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LLVM_DEBUG({
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dbgsIndent((2 + numstages - chkstage) << 1);
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dbgs() << "0x" << Twine::utohexstr(prevState) << " | 0x"
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<< Twine::utohexstr(resourceMask);
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if (combo)
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dbgs() << " | 0x" << Twine::utohexstr(combo);
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dbgs() << " = 0x" << Twine::utohexstr(ResultingResourceState) << " ";
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});
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//
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// If this is the final stage for this class
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//
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if (chkstage == 0) {
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//
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// Check if the resulting resource state can be accommodated in this
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// packet.
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// We compute resource OR prevState (originally started as origState).
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// If the result of the OR is different than origState, it implies
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// that there is at least one resource that can be used to schedule
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// thisStage in the current packet.
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// Insert ResultingResourceState into PossibleStates only if we haven't
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// processed ResultingResourceState before.
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//
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if (ResultingResourceState != prevState) {
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if (VisitedResourceStates.count(ResultingResourceState) == 0) {
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VisitedResourceStates.insert(ResultingResourceState);
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LLVM_DEBUG(dbgs()
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<< "\tResultingResourceState: 0x"
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<< Twine::utohexstr(ResultingResourceState) << "\n");
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} else {
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LLVM_DEBUG(dbgs() << "\tSkipped Add - state already seen\n");
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}
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} else {
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LLVM_DEBUG(dbgs()
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<< "\tSkipped Add - no final resources available\n");
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}
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} else {
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//
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// If the current resource can be accommodated, check the next
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// stage in InsnClass for available resources.
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//
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if (ResultingResourceState != prevState) {
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LLVM_DEBUG(dbgs() << "\n");
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AddInsnClassStages(InsnClass, ComboBitToBitsMap, chkstage - 1,
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numstages, ResultingResourceState, origState,
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VisitedResourceStates);
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} else {
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LLVM_DEBUG(dbgs() << "\tSkipped Add - no resources available\n");
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}
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}
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}
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}
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}
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|
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//
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// canMaybeAddInsnClass - Quickly verifies if an instruction of type InsnClass
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// may be a valid transition from this state i.e., can an instruction of type
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// InsnClass be added to the packet represented by this state.
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//
|
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// Note that this routine is performing conservative checks that can be
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// quickly executed acting as a filter before calling AddInsnClassStages.
|
|
// Any cases allowed through here will be caught later in AddInsnClassStages
|
|
// which performs the more expensive exact check.
|
|
//
|
|
bool State::canMaybeAddInsnClass(std::vector<unsigned> &InsnClass,
|
|
std::map<unsigned, unsigned> &ComboBitToBitsMap) const {
|
|
for (std::set<unsigned>::const_iterator SI = stateInfo.begin();
|
|
SI != stateInfo.end(); ++SI) {
|
|
// Check to see if all required resources are available.
|
|
bool available = true;
|
|
|
|
// Inspect each stage independently.
|
|
// note: This is a conservative check as we aren't checking for
|
|
// possible resource competition between the stages themselves
|
|
// The full cross product is examined later in AddInsnClass.
|
|
for (unsigned i = 0; i < InsnClass.size(); ++i) {
|
|
unsigned resources = *SI;
|
|
if ((~resources & InsnClass[i]) == 0) {
|
|
available = false;
|
|
break;
|
|
}
|
|
// Make sure _all_ resources for a combo function are available.
|
|
// note: This is a quick conservative check as it won't catch an
|
|
// unscheduleable combo if this stage is an OR expression
|
|
// containing a combo.
|
|
// These cases are caught later in AddInsnClass.
|
|
unsigned combo = ComboBitToBitsMap[InsnClass[i]];
|
|
if (combo && ((~resources & combo) != combo)) {
|
|
LLVM_DEBUG(dbgs() << "\tSkipped canMaybeAdd 0x"
|
|
<< Twine::utohexstr(resources) << " - combo op 0x"
|
|
<< Twine::utohexstr(InsnClass[i]) << " (0x"
|
|
<< Twine::utohexstr(combo)
|
|
<< ") cannot be scheduled\n");
|
|
available = false;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (available) {
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
const State &DFA::newState() {
|
|
auto IterPair = states.insert(State());
|
|
assert(IterPair.second && "State already exists");
|
|
return *IterPair.first;
|
|
}
|
|
|
|
int State::currentStateNum = 0;
|
|
|
|
DFAPacketizerEmitter::DFAPacketizerEmitter(RecordKeeper &R):
|
|
TargetName(CodeGenTarget(R).getName()), Records(R) {}
|
|
|
|
//
|
|
// writeTableAndAPI - Print out a table representing the DFA and the
|
|
// associated API to create a DFA packetizer.
|
|
//
|
|
// Format:
|
|
// DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
|
|
// transitions.
|
|
// DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable for
|
|
// the ith state.
|
|
//
|
|
//
|
|
void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName,
|
|
int numInsnClasses,
|
|
int maxResources, int numCombos, int maxStages) {
|
|
unsigned numStates = states.size();
|
|
|
|
LLVM_DEBUG(dbgs() << "-------------------------------------------------------"
|
|
"----------------------\n");
|
|
LLVM_DEBUG(dbgs() << "writeTableAndAPI\n");
|
|
LLVM_DEBUG(dbgs() << "Total states: " << numStates << "\n");
|
|
|
|
OS << "\n// " << TargetName << "DFAStateInputTable[][2] = "
|
|
<< "pairs of <Input, NextState> for all valid\n";
|
|
OS << "// transitions.\n";
|
|
OS << "// " << numStates << "\tstates\n";
|
|
OS << "// " << numInsnClasses << "\tinstruction classes\n";
|
|
OS << "// " << maxResources << "\tresources max\n";
|
|
OS << "// " << numCombos << "\tcombo resources\n";
|
|
OS << "// " << maxStages << "\tstages max\n";
|
|
OS << "const " << DFA_TBLTYPE << " "
|
|
<< TargetName << "DFAStateInputTable[][2] = {\n";
|
|
|
|
// This table provides a map to the beginning of the transitions for State s
|
|
// in DFAStateInputTable.
|
|
std::vector<int> StateEntry(numStates+1);
|
|
static const std::string SentinelEntry = "{-1, -1}";
|
|
|
|
// Tracks the total valid transitions encountered so far. It is used
|
|
// to construct the StateEntry table.
|
|
int ValidTransitions = 0;
|
|
DFA::StateSet::iterator SI = states.begin();
|
|
for (unsigned i = 0; i < numStates; ++i, ++SI) {
|
|
assert ((SI->stateNum == (int) i) && "Mismatch in state numbers");
|
|
StateEntry[i] = ValidTransitions;
|
|
for (State::TransitionMap::iterator
|
|
II = SI->Transitions.begin(), IE = SI->Transitions.end();
|
|
II != IE; ++II) {
|
|
OS << "{0x" << Twine::utohexstr(getDFAInsnInput(II->first)) << ", "
|
|
<< II->second.S->stateNum << "},\t";
|
|
}
|
|
ValidTransitions += SI->Transitions.size();
|
|
|
|
OS << " // state " << i << ": " << StateEntry[i];
|
|
if (StateEntry[i] != (ValidTransitions-1)) { // More than one transition.
|
|
OS << "-" << (ValidTransitions-1);
|
|
}
|
|
OS << "\n";
|
|
}
|
|
|
|
// Print out a sentinel entry at the end of the StateInputTable. This is
|
|
// needed to iterate over StateInputTable in DFAPacketizer::ReadTable()
|
|
OS << SentinelEntry << "\t";
|
|
OS << " // state " << numStates << ": " << ValidTransitions;
|
|
OS << "\n";
|
|
|
|
OS << "};\n\n";
|
|
OS << "// " << TargetName << "DFAStateEntryTable[i] = "
|
|
<< "Index of the first entry in DFAStateInputTable for\n";
|
|
OS << "// "
|
|
<< "the ith state.\n";
|
|
OS << "// " << numStates << " states\n";
|
|
OS << "const unsigned int " << TargetName << "DFAStateEntryTable[] = {\n";
|
|
|
|
unsigned lastState = 0;
|
|
for (unsigned i = 0; i < numStates; ++i) {
|
|
if (i && ((i % 10) == 0)) {
|
|
lastState = i-1;
|
|
OS << " // states " << (i-10) << ":" << lastState << "\n";
|
|
}
|
|
OS << StateEntry[i] << ", ";
|
|
}
|
|
// Print out the index to the sentinel entry in StateInputTable
|
|
OS << ValidTransitions << ", ";
|
|
OS << " // states " << (lastState+1) << ":" << numStates << "\n";
|
|
OS << "};\n";
|
|
|
|
// Generate the resource transition table.
|
|
OS << "const unsigned " << TargetName
|
|
<< "DFAResourceTransitionTable[][2] = { \n";
|
|
int N = 0;
|
|
StateEntry.clear();
|
|
for (const State &S : states) {
|
|
for (auto &KV : S.Transitions) {
|
|
StateEntry.push_back(N);
|
|
for (std::pair<unsigned, unsigned> &T : KV.second.ResourceTransitions) {
|
|
OS << "{0x" << utohexstr(T.first) << ", 0x" << utohexstr(T.second)
|
|
<< "}, ";
|
|
++N;
|
|
}
|
|
}
|
|
OS << "\n ";
|
|
}
|
|
// Add a sentinel entry to terminate the search.
|
|
StateEntry.push_back(N);
|
|
OS << "\n {~0U,~0U}\n};\n\n";
|
|
|
|
OS << "// " << TargetName << "DFAResourceTransitionEntryTable[i] = "
|
|
<< "Index of the first entry in DFAResourceTransitionTable for\n";
|
|
OS << "// the ith transition.\n";
|
|
OS << "const unsigned int " << TargetName
|
|
<< "DFAResourceTransitionEntryTable[] = { \n";
|
|
|
|
N = 0;
|
|
for (int S : StateEntry) {
|
|
OS << S << ",";
|
|
if (N++ % 10 == 0)
|
|
OS << "\n ";
|
|
}
|
|
OS << "\n ~0U\n};\n";
|
|
}
|
|
|
|
//
|
|
// collectAllFuncUnits - Construct a map of function unit names to bits.
|
|
//
|
|
int DFAPacketizerEmitter::collectAllFuncUnits(
|
|
std::vector<Record*> &ProcItinList,
|
|
std::map<std::string, unsigned> &FUNameToBitsMap,
|
|
int &maxFUs,
|
|
raw_ostream &OS) {
|
|
LLVM_DEBUG(dbgs() << "-------------------------------------------------------"
|
|
"----------------------\n");
|
|
LLVM_DEBUG(dbgs() << "collectAllFuncUnits");
|
|
LLVM_DEBUG(dbgs() << " (" << ProcItinList.size() << " itineraries)\n");
|
|
|
|
int totalFUs = 0;
|
|
// Parse functional units for all the itineraries.
|
|
for (unsigned i = 0, N = ProcItinList.size(); i < N; ++i) {
|
|
Record *Proc = ProcItinList[i];
|
|
std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU");
|
|
|
|
LLVM_DEBUG(dbgs() << " FU:" << i << " (" << FUs.size() << " FUs) "
|
|
<< Proc->getName());
|
|
|
|
// Convert macros to bits for each stage.
|
|
unsigned numFUs = FUs.size();
|
|
for (unsigned j = 0; j < numFUs; ++j) {
|
|
assert ((j < DFA_MAX_RESOURCES) &&
|
|
"Exceeded maximum number of representable resources");
|
|
unsigned FuncResources = (unsigned) (1U << j);
|
|
FUNameToBitsMap[FUs[j]->getName()] = FuncResources;
|
|
LLVM_DEBUG(dbgs() << " " << FUs[j]->getName() << ":0x"
|
|
<< Twine::utohexstr(FuncResources));
|
|
}
|
|
if (((int) numFUs) > maxFUs) {
|
|
maxFUs = numFUs;
|
|
}
|
|
totalFUs += numFUs;
|
|
LLVM_DEBUG(dbgs() << "\n");
|
|
}
|
|
return totalFUs;
|
|
}
|
|
|
|
//
|
|
// collectAllComboFuncs - Construct a map from a combo function unit bit to
|
|
// the bits of all included functional units.
|
|
//
|
|
int DFAPacketizerEmitter::collectAllComboFuncs(
|
|
std::vector<Record*> &ComboFuncList,
|
|
std::map<std::string, unsigned> &FUNameToBitsMap,
|
|
std::map<unsigned, unsigned> &ComboBitToBitsMap,
|
|
raw_ostream &OS) {
|
|
LLVM_DEBUG(dbgs() << "-------------------------------------------------------"
|
|
"----------------------\n");
|
|
LLVM_DEBUG(dbgs() << "collectAllComboFuncs");
|
|
LLVM_DEBUG(dbgs() << " (" << ComboFuncList.size() << " sets)\n");
|
|
|
|
int numCombos = 0;
|
|
for (unsigned i = 0, N = ComboFuncList.size(); i < N; ++i) {
|
|
Record *Func = ComboFuncList[i];
|
|
std::vector<Record*> FUs = Func->getValueAsListOfDefs("CFD");
|
|
|
|
LLVM_DEBUG(dbgs() << " CFD:" << i << " (" << FUs.size() << " combo FUs) "
|
|
<< Func->getName() << "\n");
|
|
|
|
// Convert macros to bits for each stage.
|
|
for (unsigned j = 0, N = FUs.size(); j < N; ++j) {
|
|
assert ((j < DFA_MAX_RESOURCES) &&
|
|
"Exceeded maximum number of DFA resources");
|
|
Record *FuncData = FUs[j];
|
|
Record *ComboFunc = FuncData->getValueAsDef("TheComboFunc");
|
|
const std::vector<Record*> &FuncList =
|
|
FuncData->getValueAsListOfDefs("FuncList");
|
|
const std::string &ComboFuncName = ComboFunc->getName();
|
|
unsigned ComboBit = FUNameToBitsMap[ComboFuncName];
|
|
unsigned ComboResources = ComboBit;
|
|
LLVM_DEBUG(dbgs() << " combo: " << ComboFuncName << ":0x"
|
|
<< Twine::utohexstr(ComboResources) << "\n");
|
|
for (unsigned k = 0, M = FuncList.size(); k < M; ++k) {
|
|
std::string FuncName = FuncList[k]->getName();
|
|
unsigned FuncResources = FUNameToBitsMap[FuncName];
|
|
LLVM_DEBUG(dbgs() << " " << FuncName << ":0x"
|
|
<< Twine::utohexstr(FuncResources) << "\n");
|
|
ComboResources |= FuncResources;
|
|
}
|
|
ComboBitToBitsMap[ComboBit] = ComboResources;
|
|
numCombos++;
|
|
LLVM_DEBUG(dbgs() << " => combo bits: " << ComboFuncName << ":0x"
|
|
<< Twine::utohexstr(ComboBit) << " = 0x"
|
|
<< Twine::utohexstr(ComboResources) << "\n");
|
|
}
|
|
}
|
|
return numCombos;
|
|
}
|
|
|
|
//
|
|
// collectOneInsnClass - Populate allInsnClasses with one instruction class
|
|
//
|
|
int DFAPacketizerEmitter::collectOneInsnClass(const std::string &ProcName,
|
|
std::vector<Record*> &ProcItinList,
|
|
std::map<std::string, unsigned> &FUNameToBitsMap,
|
|
Record *ItinData,
|
|
raw_ostream &OS) {
|
|
const std::vector<Record*> &StageList =
|
|
ItinData->getValueAsListOfDefs("Stages");
|
|
|
|
// The number of stages.
|
|
unsigned NStages = StageList.size();
|
|
|
|
LLVM_DEBUG(dbgs() << " " << ItinData->getValueAsDef("TheClass")->getName()
|
|
<< "\n");
|
|
|
|
std::vector<unsigned> UnitBits;
|
|
|
|
// Compute the bitwise or of each unit used in this stage.
|
|
for (unsigned i = 0; i < NStages; ++i) {
|
|
const Record *Stage = StageList[i];
|
|
|
|
// Get unit list.
|
|
const std::vector<Record*> &UnitList =
|
|
Stage->getValueAsListOfDefs("Units");
|
|
|
|
LLVM_DEBUG(dbgs() << " stage:" << i << " [" << UnitList.size()
|
|
<< " units]:");
|
|
unsigned dbglen = 26; // cursor after stage dbgs
|
|
|
|
// Compute the bitwise or of each unit used in this stage.
|
|
unsigned UnitBitValue = 0;
|
|
for (unsigned j = 0, M = UnitList.size(); j < M; ++j) {
|
|
// Conduct bitwise or.
|
|
std::string UnitName = UnitList[j]->getName();
|
|
LLVM_DEBUG(dbgs() << " " << j << ":" << UnitName);
|
|
dbglen += 3 + UnitName.length();
|
|
assert(FUNameToBitsMap.count(UnitName));
|
|
UnitBitValue |= FUNameToBitsMap[UnitName];
|
|
}
|
|
|
|
if (UnitBitValue != 0)
|
|
UnitBits.push_back(UnitBitValue);
|
|
|
|
while (dbglen <= 64) { // line up bits dbgs
|
|
dbglen += 8;
|
|
LLVM_DEBUG(dbgs() << "\t");
|
|
}
|
|
LLVM_DEBUG(dbgs() << " (bits: 0x" << Twine::utohexstr(UnitBitValue)
|
|
<< ")\n");
|
|
}
|
|
|
|
if (!UnitBits.empty())
|
|
allInsnClasses.push_back(UnitBits);
|
|
|
|
LLVM_DEBUG({
|
|
dbgs() << " ";
|
|
dbgsInsnClass(UnitBits);
|
|
dbgs() << "\n";
|
|
});
|
|
|
|
return NStages;
|
|
}
|
|
|
|
//
|
|
// collectAllInsnClasses - Populate allInsnClasses which is a set of units
|
|
// used in each stage.
|
|
//
|
|
int DFAPacketizerEmitter::collectAllInsnClasses(const std::string &ProcName,
|
|
std::vector<Record*> &ProcItinList,
|
|
std::map<std::string, unsigned> &FUNameToBitsMap,
|
|
std::vector<Record*> &ItinDataList,
|
|
int &maxStages,
|
|
raw_ostream &OS) {
|
|
// Collect all instruction classes.
|
|
unsigned M = ItinDataList.size();
|
|
|
|
int numInsnClasses = 0;
|
|
LLVM_DEBUG(dbgs() << "-------------------------------------------------------"
|
|
"----------------------\n"
|
|
<< "collectAllInsnClasses " << ProcName << " (" << M
|
|
<< " classes)\n");
|
|
|
|
// Collect stages for each instruction class for all itinerary data
|
|
for (unsigned j = 0; j < M; j++) {
|
|
Record *ItinData = ItinDataList[j];
|
|
int NStages = collectOneInsnClass(ProcName, ProcItinList,
|
|
FUNameToBitsMap, ItinData, OS);
|
|
if (NStages > maxStages) {
|
|
maxStages = NStages;
|
|
}
|
|
numInsnClasses++;
|
|
}
|
|
return numInsnClasses;
|
|
}
|
|
|
|
//
|
|
// Run the worklist algorithm to generate the DFA.
|
|
//
|
|
void DFAPacketizerEmitter::run(raw_ostream &OS) {
|
|
OS << "\n"
|
|
<< "#include \"llvm/CodeGen/DFAPacketizer.h\"\n";
|
|
OS << "namespace llvm {\n";
|
|
|
|
OS << "\n// Input format:\n";
|
|
OS << "#define DFA_MAX_RESTERMS " << DFA_MAX_RESTERMS
|
|
<< "\t// maximum AND'ed resource terms\n";
|
|
OS << "#define DFA_MAX_RESOURCES " << DFA_MAX_RESOURCES
|
|
<< "\t// maximum resource bits in one term\n";
|
|
|
|
// Collect processor iteraries.
|
|
std::vector<Record*> ProcItinList =
|
|
Records.getAllDerivedDefinitions("ProcessorItineraries");
|
|
|
|
std::unordered_map<std::string, std::vector<Record*>> ItinsByNamespace;
|
|
for (Record *R : ProcItinList)
|
|
ItinsByNamespace[R->getValueAsString("PacketizerNamespace")].push_back(R);
|
|
|
|
for (auto &KV : ItinsByNamespace)
|
|
emitForItineraries(OS, KV.second, KV.first);
|
|
OS << "} // end namespace llvm\n";
|
|
}
|
|
|
|
void DFAPacketizerEmitter::emitForItineraries(
|
|
raw_ostream &OS, std::vector<Record *> &ProcItinList,
|
|
std::string DFAName) {
|
|
//
|
|
// Collect the Functional units.
|
|
//
|
|
std::map<std::string, unsigned> FUNameToBitsMap;
|
|
int maxResources = 0;
|
|
collectAllFuncUnits(ProcItinList,
|
|
FUNameToBitsMap, maxResources, OS);
|
|
|
|
//
|
|
// Collect the Combo Functional units.
|
|
//
|
|
std::map<unsigned, unsigned> ComboBitToBitsMap;
|
|
std::vector<Record*> ComboFuncList =
|
|
Records.getAllDerivedDefinitions("ComboFuncUnits");
|
|
int numCombos = collectAllComboFuncs(ComboFuncList,
|
|
FUNameToBitsMap, ComboBitToBitsMap, OS);
|
|
|
|
//
|
|
// Collect the itineraries.
|
|
//
|
|
int maxStages = 0;
|
|
int numInsnClasses = 0;
|
|
for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
|
|
Record *Proc = ProcItinList[i];
|
|
|
|
// Get processor itinerary name.
|
|
const std::string &ProcName = Proc->getName();
|
|
|
|
// Skip default.
|
|
if (ProcName == "NoItineraries")
|
|
continue;
|
|
|
|
// Sanity check for at least one instruction itinerary class.
|
|
unsigned NItinClasses =
|
|
Records.getAllDerivedDefinitions("InstrItinClass").size();
|
|
if (NItinClasses == 0)
|
|
return;
|
|
|
|
// Get itinerary data list.
|
|
std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
|
|
|
|
// Collect all instruction classes
|
|
numInsnClasses += collectAllInsnClasses(ProcName, ProcItinList,
|
|
FUNameToBitsMap, ItinDataList, maxStages, OS);
|
|
}
|
|
|
|
//
|
|
// Run a worklist algorithm to generate the DFA.
|
|
//
|
|
DFA D;
|
|
const State *Initial = &D.newState();
|
|
Initial->isInitial = true;
|
|
Initial->stateInfo.insert(0x0);
|
|
SmallVector<const State*, 32> WorkList;
|
|
std::map<std::set<unsigned>, const State*> Visited;
|
|
|
|
WorkList.push_back(Initial);
|
|
|
|
//
|
|
// Worklist algorithm to create a DFA for processor resource tracking.
|
|
// C = {set of InsnClasses}
|
|
// Begin with initial node in worklist. Initial node does not have
|
|
// any consumed resources,
|
|
// ResourceState = 0x0
|
|
// Visited = {}
|
|
// While worklist != empty
|
|
// S = first element of worklist
|
|
// For every instruction class C
|
|
// if we can accommodate C in S:
|
|
// S' = state with resource states = {S Union C}
|
|
// Add a new transition: S x C -> S'
|
|
// If S' is not in Visited:
|
|
// Add S' to worklist
|
|
// Add S' to Visited
|
|
//
|
|
while (!WorkList.empty()) {
|
|
const State *current = WorkList.pop_back_val();
|
|
LLVM_DEBUG({
|
|
dbgs() << "---------------------\n";
|
|
dbgs() << "Processing state: " << current->stateNum << " - ";
|
|
dbgsStateInfo(current->stateInfo);
|
|
dbgs() << "\n";
|
|
});
|
|
for (unsigned i = 0; i < allInsnClasses.size(); i++) {
|
|
std::vector<unsigned> InsnClass = allInsnClasses[i];
|
|
LLVM_DEBUG({
|
|
dbgs() << i << " ";
|
|
dbgsInsnClass(InsnClass);
|
|
dbgs() << "\n";
|
|
});
|
|
|
|
std::set<unsigned> NewStateResources;
|
|
//
|
|
// If we haven't already created a transition for this input
|
|
// and the state can accommodate this InsnClass, create a transition.
|
|
//
|
|
if (!current->hasTransition(InsnClass) &&
|
|
current->canMaybeAddInsnClass(InsnClass, ComboBitToBitsMap)) {
|
|
const State *NewState = nullptr;
|
|
std::vector<std::pair<unsigned, unsigned>> TransitionInfo;
|
|
current->AddInsnClass(InsnClass, ComboBitToBitsMap, NewStateResources,
|
|
TransitionInfo);
|
|
if (NewStateResources.empty()) {
|
|
LLVM_DEBUG(dbgs() << " Skipped - no new states generated\n");
|
|
continue;
|
|
}
|
|
|
|
LLVM_DEBUG({
|
|
dbgs() << "\t";
|
|
dbgsStateInfo(NewStateResources);
|
|
dbgs() << "\n";
|
|
});
|
|
|
|
//
|
|
// If we have seen this state before, then do not create a new state.
|
|
//
|
|
auto VI = Visited.find(NewStateResources);
|
|
if (VI != Visited.end()) {
|
|
NewState = VI->second;
|
|
LLVM_DEBUG({
|
|
dbgs() << "\tFound existing state: " << NewState->stateNum
|
|
<< " - ";
|
|
dbgsStateInfo(NewState->stateInfo);
|
|
dbgs() << "\n";
|
|
});
|
|
} else {
|
|
NewState = &D.newState();
|
|
NewState->stateInfo = NewStateResources;
|
|
Visited[NewStateResources] = NewState;
|
|
WorkList.push_back(NewState);
|
|
LLVM_DEBUG({
|
|
dbgs() << "\tAccepted new state: " << NewState->stateNum << " - ";
|
|
dbgsStateInfo(NewState->stateInfo);
|
|
dbgs() << "\n";
|
|
});
|
|
}
|
|
|
|
current->addTransition(InsnClass, NewState, TransitionInfo);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Print out the table.
|
|
D.writeTableAndAPI(OS, TargetName + DFAName, numInsnClasses, maxResources,
|
|
numCombos, maxStages);
|
|
|
|
OS << "} // end namespace llvm\n";
|
|
|
|
std::string SubTargetClassName = TargetName + "GenSubtargetInfo";
|
|
OS << "namespace llvm {\n";
|
|
OS << "DFAPacketizer *" << SubTargetClassName << "::"
|
|
<< "create" << DFAName
|
|
<< "DFAPacketizer(const InstrItineraryData *IID) const {\n"
|
|
<< " return new DFAPacketizer(IID, " << TargetName << DFAName
|
|
<< "DFAStateInputTable, " << TargetName << DFAName
|
|
<< "DFAStateEntryTable, " << TargetName << DFAName
|
|
<< "DFAResourceTransitionTable, " << TargetName << DFAName
|
|
<< "DFAResourceTransitionEntryTable"
|
|
<< ");\n}\n\n";
|
|
}
|
|
|
|
namespace llvm {
|
|
|
|
void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS) {
|
|
emitSourceFileHeader("Target DFA Packetizer Tables", OS);
|
|
DFAPacketizerEmitter(RK).run(OS);
|
|
}
|
|
|
|
} // end namespace llvm
|