llvm-project/llvm/test/CodeGen
Sam Parker 1c803f5988 [ARM] Attempt to fix arm selfhost bots after rL347191
llvm-svn: 347238
2018-11-19 18:08:46 +00:00
..
AArch64 Subject: [PATCH] [CodeGen] Add pass to combine interleaved loads. 2018-11-19 14:26:10 +00:00
AMDGPU [AMDGPU] Convert insert_vector_elt into set of selects 2018-11-19 17:39:20 +00:00
ARC
ARM [ARM] Attempt to fix arm selfhost bots after rL347191 2018-11-19 18:08:46 +00:00
AVR [AVR] Reorder the CHECK lines in directmem.ll to match current trunk 2018-11-09 23:17:59 +00:00
BPF
Generic Moved dag-combine-select-undef.ll into amdgpu. NFC. 2018-11-17 00:17:15 +00:00
Hexagon [Hexagon] make test immune to improvements in undef simplification 2018-11-19 15:34:09 +00:00
Inputs
Lanai
MIR [Power9] Allow gpr callee saved spills in prologue to vectors registers 2018-11-09 16:36:24 +00:00
MSP430 [MSP430] Optimize srl/sra in case of A >> (8 + N) 2018-11-19 10:43:02 +00:00
Mips [DAGCombiner][X86][Mips] Enable combineShuffleOfScalars to run between vector op legalization and DAG legalization. Fix bad one use check in combineShuffleOfScalars 2018-11-09 18:04:34 +00:00
NVPTX
Nios2
PowerPC [PowerPC][NFC] Add tests for vector fp <-> int conversions 2018-11-16 20:24:10 +00:00
RISCV [RISCV] Constant materialisation for RV64I 2018-11-16 10:14:16 +00:00
SPARC Relax fast register allocator related test cases; NFC 2018-10-29 20:10:42 +00:00
SystemZ [SystemZ] make test immune to improvements in undef simplification 2018-11-18 16:50:44 +00:00
Thumb [SelectionDAG] swap select_cc operands to enable folding 2018-11-09 11:09:40 +00:00
Thumb2 [ARM] Enable spilling of the hGPR register class in Thumb2 2018-11-08 13:02:10 +00:00
WebAssembly [WebAssembly] replaced .param/.result by .functype 2018-11-19 17:10:36 +00:00
WinCFGuard
WinEH
X86 [SelectionDAG] simplify vector select with undef operand(s) 2018-11-19 17:06:05 +00:00
XCore Relax fast register allocator related test cases; NFC 2018-10-29 20:10:42 +00:00