forked from OSchip/llvm-project
303 lines
12 KiB
LLVM
303 lines
12 KiB
LLVM
; RUN: opt < %s -instcombine -S | FileCheck %s
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;; MASKED LOADS
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; If the mask isn't constant, do nothing.
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define <4 x float> @mload(i8* %f, <4 x i32> %mask) {
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%ld = tail call <4 x float> @llvm.x86.avx.maskload.ps(i8* %f, <4 x i32> %mask)
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ret <4 x float> %ld
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; CHECK-LABEL: @mload(
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; CHECK-NEXT: %ld = tail call <4 x float> @llvm.x86.avx.maskload.ps(i8* %f, <4 x i32> %mask)
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; CHECK-NEXT: ret <4 x float> %ld
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}
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; Zero mask returns a zero vector.
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define <4 x float> @mload_zeros(i8* %f) {
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%ld = tail call <4 x float> @llvm.x86.avx.maskload.ps(i8* %f, <4 x i32> zeroinitializer)
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ret <4 x float> %ld
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; CHECK-LABEL: @mload_zeros(
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; CHECK-NEXT: ret <4 x float> zeroinitializer
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}
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; Only the sign bit matters.
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define <4 x float> @mload_fake_ones(i8* %f) {
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%ld = tail call <4 x float> @llvm.x86.avx.maskload.ps(i8* %f, <4 x i32> <i32 1, i32 2, i32 3, i32 2147483647>)
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ret <4 x float> %ld
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; CHECK-LABEL: @mload_fake_ones(
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; CHECK-NEXT: ret <4 x float> zeroinitializer
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}
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; All mask bits are set, so this is just a vector load.
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define <4 x float> @mload_real_ones(i8* %f) {
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%ld = tail call <4 x float> @llvm.x86.avx.maskload.ps(i8* %f, <4 x i32> <i32 -1, i32 -2, i32 -3, i32 2147483648>)
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ret <4 x float> %ld
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; CHECK-LABEL: @mload_real_ones(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x float>*
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; CHECK-NEXT: %unmaskedload = load <4 x float>, <4 x float>* %castvec
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; CHECK-NEXT: ret <4 x float> %unmaskedload
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}
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; It's a constant mask, so convert to an LLVM intrinsic. The backend should optimize further.
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define <4 x float> @mload_one_one(i8* %f) {
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%ld = tail call <4 x float> @llvm.x86.avx.maskload.ps(i8* %f, <4 x i32> <i32 0, i32 0, i32 0, i32 -1>)
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ret <4 x float> %ld
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; CHECK-LABEL: @mload_one_one(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x float>*
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; CHECK-NEXT: %1 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %castvec, i32 1, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> zeroinitializer)
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; CHECK-NEXT: ret <4 x float> %1
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}
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; Try doubles.
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define <2 x double> @mload_one_one_double(i8* %f) {
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%ld = tail call <2 x double> @llvm.x86.avx.maskload.pd(i8* %f, <2 x i64> <i64 -1, i64 0>)
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ret <2 x double> %ld
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; CHECK-LABEL: @mload_one_one_double(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <2 x double>*
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; CHECK-NEXT: %1 = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %castvec, i32 1, <2 x i1> <i1 true, i1 false>, <2 x double> zeroinitializer)
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; CHECK-NEXT: ret <2 x double> %1
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}
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; Try 256-bit FP ops.
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define <8 x float> @mload_v8f32(i8* %f) {
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%ld = tail call <8 x float> @llvm.x86.avx.maskload.ps.256(i8* %f, <8 x i32> <i32 0, i32 0, i32 0, i32 -1, i32 0, i32 0, i32 0, i32 0>)
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ret <8 x float> %ld
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; CHECK-LABEL: @mload_v8f32(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <8 x float>*
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; CHECK-NEXT: %1 = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* %castvec, i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x float> zeroinitializer)
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; CHECK-NEXT: ret <8 x float> %1
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}
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define <4 x double> @mload_v4f64(i8* %f) {
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%ld = tail call <4 x double> @llvm.x86.avx.maskload.pd.256(i8* %f, <4 x i64> <i64 -1, i64 0, i64 0, i64 0>)
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ret <4 x double> %ld
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; CHECK-LABEL: @mload_v4f64(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x double>*
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; CHECK-NEXT: %1 = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* %castvec, i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x double> zeroinitializer)
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; CHECK-NEXT: ret <4 x double> %1
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}
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; Try the AVX2 variants.
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define <4 x i32> @mload_v4i32(i8* %f) {
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%ld = tail call <4 x i32> @llvm.x86.avx2.maskload.d(i8* %f, <4 x i32> <i32 0, i32 0, i32 0, i32 -1>)
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ret <4 x i32> %ld
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; CHECK-LABEL: @mload_v4i32(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x i32>*
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; CHECK-NEXT: %1 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %castvec, i32 1, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x i32> zeroinitializer)
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; CHECK-NEXT: ret <4 x i32> %1
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}
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define <2 x i64> @mload_v2i64(i8* %f) {
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%ld = tail call <2 x i64> @llvm.x86.avx2.maskload.q(i8* %f, <2 x i64> <i64 -1, i64 0>)
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ret <2 x i64> %ld
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; CHECK-LABEL: @mload_v2i64(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <2 x i64>*
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; CHECK-NEXT: %1 = call <2 x i64> @llvm.masked.load.v2i64.p0v2i64(<2 x i64>* %castvec, i32 1, <2 x i1> <i1 true, i1 false>, <2 x i64> zeroinitializer)
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; CHECK-NEXT: ret <2 x i64> %1
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}
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define <8 x i32> @mload_v8i32(i8* %f) {
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%ld = tail call <8 x i32> @llvm.x86.avx2.maskload.d.256(i8* %f, <8 x i32> <i32 0, i32 0, i32 0, i32 -1, i32 0, i32 0, i32 0, i32 0>)
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ret <8 x i32> %ld
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; CHECK-LABEL: @mload_v8i32(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <8 x i32>*
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; CHECK-NEXT: %1 = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %castvec, i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i32> zeroinitializer)
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; CHECK-NEXT: ret <8 x i32> %1
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}
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define <4 x i64> @mload_v4i64(i8* %f) {
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%ld = tail call <4 x i64> @llvm.x86.avx2.maskload.q.256(i8* %f, <4 x i64> <i64 -1, i64 0, i64 0, i64 0>)
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ret <4 x i64> %ld
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; CHECK-LABEL: @mload_v4i64(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x i64>*
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; CHECK-NEXT: %1 = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* %castvec, i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i64> zeroinitializer)
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; CHECK-NEXT: ret <4 x i64> %1
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}
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;; MASKED STORES
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; If the mask isn't constant, do nothing.
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define void @mstore(i8* %f, <4 x i32> %mask, <4 x float> %v) {
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tail call void @llvm.x86.avx.maskstore.ps(i8* %f, <4 x i32> %mask, <4 x float> %v)
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ret void
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; CHECK-LABEL: @mstore(
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; CHECK-NEXT: tail call void @llvm.x86.avx.maskstore.ps(i8* %f, <4 x i32> %mask, <4 x float> %v)
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; CHECK-NEXT: ret void
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}
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; Zero mask is a nop.
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define void @mstore_zeros(i8* %f, <4 x float> %v) {
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tail call void @llvm.x86.avx.maskstore.ps(i8* %f, <4 x i32> zeroinitializer, <4 x float> %v)
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ret void
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; CHECK-LABEL: @mstore_zeros(
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; CHECK-NEXT: ret void
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}
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; Only the sign bit matters.
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define void @mstore_fake_ones(i8* %f, <4 x float> %v) {
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tail call void @llvm.x86.avx.maskstore.ps(i8* %f, <4 x i32> <i32 1, i32 2, i32 3, i32 2147483647>, <4 x float> %v)
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ret void
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; CHECK-LABEL: @mstore_fake_ones(
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; CHECK-NEXT: ret void
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}
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; All mask bits are set, so this is just a vector store.
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define void @mstore_real_ones(i8* %f, <4 x float> %v) {
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tail call void @llvm.x86.avx.maskstore.ps(i8* %f, <4 x i32> <i32 -1, i32 -2, i32 -3, i32 -2147483648>, <4 x float> %v)
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ret void
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; CHECK-LABEL: @mstore_real_ones(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x float>*
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; CHECK-NEXT: store <4 x float> %v, <4 x float>* %castvec
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; CHECK-NEXT: ret void
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}
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; It's a constant mask, so convert to an LLVM intrinsic. The backend should optimize further.
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define void @mstore_one_one(i8* %f, <4 x float> %v) {
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tail call void @llvm.x86.avx.maskstore.ps(i8* %f, <4 x i32> <i32 0, i32 0, i32 0, i32 -1>, <4 x float> %v)
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ret void
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; CHECK-LABEL: @mstore_one_one(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x float>*
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; CHECK-NEXT: call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %v, <4 x float>* %castvec, i32 1, <4 x i1> <i1 false, i1 false, i1 false, i1 true>)
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; CHECK-NEXT: ret void
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}
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; Try doubles.
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define void @mstore_one_one_double(i8* %f, <2 x double> %v) {
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tail call void @llvm.x86.avx.maskstore.pd(i8* %f, <2 x i64> <i64 -1, i64 0>, <2 x double> %v)
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ret void
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; CHECK-LABEL: @mstore_one_one_double(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <2 x double>*
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; CHECK-NEXT: call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> %v, <2 x double>* %castvec, i32 1, <2 x i1> <i1 true, i1 false>)
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; CHECK-NEXT: ret void
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}
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; Try 256-bit FP ops.
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define void @mstore_v8f32(i8* %f, <8 x float> %v) {
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tail call void @llvm.x86.avx.maskstore.ps.256(i8* %f, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 -1, i32 -2, i32 -3, i32 -4>, <8 x float> %v)
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ret void
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; CHECK-LABEL: @mstore_v8f32(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <8 x float>*
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; CHECK-NEXT: call void @llvm.masked.store.v8f32.p0v8f32(<8 x float> %v, <8 x float>* %castvec, i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>)
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; CHECK-NEXT: ret void
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}
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define void @mstore_v4f64(i8* %f, <4 x double> %v) {
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tail call void @llvm.x86.avx.maskstore.pd.256(i8* %f, <4 x i64> <i64 -1, i64 0, i64 1, i64 2>, <4 x double> %v)
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ret void
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; CHECK-LABEL: @mstore_v4f64(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x double>*
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; CHECK-NEXT: call void @llvm.masked.store.v4f64.p0v4f64(<4 x double> %v, <4 x double>* %castvec, i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>)
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; CHECK-NEXT: ret void
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}
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; Try the AVX2 variants.
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define void @mstore_v4i32(i8* %f, <4 x i32> %v) {
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tail call void @llvm.x86.avx2.maskstore.d(i8* %f, <4 x i32> <i32 0, i32 1, i32 -1, i32 -2>, <4 x i32> %v)
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ret void
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; CHECK-LABEL: @mstore_v4i32(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x i32>*
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; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %v, <4 x i32>* %castvec, i32 1, <4 x i1> <i1 false, i1 false, i1 true, i1 true>)
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; CHECK-NEXT: ret void
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}
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define void @mstore_v2i64(i8* %f, <2 x i64> %v) {
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tail call void @llvm.x86.avx2.maskstore.q(i8* %f, <2 x i64> <i64 -1, i64 0>, <2 x i64> %v)
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ret void
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; CHECK-LABEL: @mstore_v2i64(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <2 x i64>*
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; CHECK-NEXT: call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %v, <2 x i64>* %castvec, i32 1, <2 x i1> <i1 true, i1 false>)
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; CHECK-NEXT: ret void
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}
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define void @mstore_v8i32(i8* %f, <8 x i32> %v) {
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tail call void @llvm.x86.avx2.maskstore.d.256(i8* %f, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 -1, i32 -2, i32 -3, i32 -4>, <8 x i32> %v)
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ret void
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; CHECK-LABEL: @mstore_v8i32(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <8 x i32>*
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; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %v, <8 x i32>* %castvec, i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>)
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; CHECK-NEXT: ret void
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}
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define void @mstore_v4i64(i8* %f, <4 x i64> %v) {
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tail call void @llvm.x86.avx2.maskstore.q.256(i8* %f, <4 x i64> <i64 -1, i64 0, i64 1, i64 2>, <4 x i64> %v)
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ret void
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; CHECK-LABEL: @mstore_v4i64(
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; CHECK-NEXT: %castvec = bitcast i8* %f to <4 x i64>*
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; CHECK-NEXT: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %castvec, i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>)
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; CHECK-NEXT: ret void
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}
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; The original SSE2 masked store variant.
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define void @mstore_v16i8_sse2_zeros(<16 x i8> %d, i8* %p) {
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tail call void @llvm.x86.sse2.maskmov.dqu(<16 x i8> %d, <16 x i8> zeroinitializer, i8* %p)
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ret void
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; CHECK-LABEL: @mstore_v16i8_sse2_zeros(
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; CHECK-NEXT: ret void
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}
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declare <4 x float> @llvm.x86.avx.maskload.ps(i8*, <4 x i32>)
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declare <2 x double> @llvm.x86.avx.maskload.pd(i8*, <2 x i64>)
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declare <8 x float> @llvm.x86.avx.maskload.ps.256(i8*, <8 x i32>)
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declare <4 x double> @llvm.x86.avx.maskload.pd.256(i8*, <4 x i64>)
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declare <4 x i32> @llvm.x86.avx2.maskload.d(i8*, <4 x i32>)
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declare <2 x i64> @llvm.x86.avx2.maskload.q(i8*, <2 x i64>)
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declare <8 x i32> @llvm.x86.avx2.maskload.d.256(i8*, <8 x i32>)
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declare <4 x i64> @llvm.x86.avx2.maskload.q.256(i8*, <4 x i64>)
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declare void @llvm.x86.avx.maskstore.ps(i8*, <4 x i32>, <4 x float>)
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declare void @llvm.x86.avx.maskstore.pd(i8*, <2 x i64>, <2 x double>)
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declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x i32>, <8 x float>)
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declare void @llvm.x86.avx.maskstore.pd.256(i8*, <4 x i64>, <4 x double>)
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declare void @llvm.x86.avx2.maskstore.d(i8*, <4 x i32>, <4 x i32>)
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declare void @llvm.x86.avx2.maskstore.q(i8*, <2 x i64>, <2 x i64>)
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declare void @llvm.x86.avx2.maskstore.d.256(i8*, <8 x i32>, <8 x i32>)
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declare void @llvm.x86.avx2.maskstore.q.256(i8*, <4 x i64>, <4 x i64>)
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declare void @llvm.x86.sse2.maskmov.dqu(<16 x i8>, <16 x i8>, i8*)
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