llvm-project/mlir
Eugene Zhulenev 86ad0af870 [mlir:Async] Implement recursive async work splitting for scf.parallel operation (async-parallel-for pass)
Depends On D104780

Recursive work splitting instead of sequential async tasks submission gives ~20%-30% speedup in microbenchmarks.

Algorithm outline:
1. Collapse scf.parallel dimensions into a single dimension
2. Compute the block size for the parallel operations from the 1d problem size
3. Launch parallel tasks
4. Each parallel task reconstructs its own bounds in the original multi-dimensional iteration space
5. Each parallel task computes the original parallel operation body using scf.for loop nest

Reviewed By: herhut

Differential Revision: https://reviews.llvm.org/D104850
2021-06-25 10:34:39 -07:00
..
cmake/modules [MLIR] Make MLIR cmake variable names consistent 2021-05-24 08:43:10 +05:30
docs Fix typo in Toy Tutorial Ch-4 2021-06-23 03:33:34 +00:00
examples [MLIR][NFC] Rename MemRefDataFlow -> AffineScalarReplacement 2021-06-14 17:52:53 +05:30
include [mlir:Async] Implement recursive async work splitting for scf.parallel operation (async-parallel-for pass) 2021-06-25 10:34:39 -07:00
lib [mlir:Async] Implement recursive async work splitting for scf.parallel operation (async-parallel-for pass) 2021-06-25 10:34:39 -07:00
python [mlir][linalg][python] Add shape-only tensor support to OpDSL. 2021-06-24 14:11:15 +00:00
test [mlir:Async] Implement recursive async work splitting for scf.parallel operation (async-parallel-for pass) 2021-06-25 10:34:39 -07:00
tools [mlir][linalg][python] Add attribute support to the YAML codegen. 2021-06-24 12:33:48 +00:00
unittests [mlir][OpGen] Cache Identifiers for known attribute names in AbstractOperation. 2021-06-22 19:56:05 +00:00
utils [MLIR] Introduce scf.execute_region op 2021-06-18 15:22:33 +05:30
.clang-format
.clang-tidy NFC: .clang-tidy: Inherit configs from parents to improve maintainability 2021-06-08 08:25:59 -07:00
CMakeLists.txt [MLIR] Drop old cmake var names 2021-05-24 15:30:01 +05:30
LICENSE.TXT
README.md

README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.