forked from OSchip/llvm-project
150 lines
5.8 KiB
LLVM
150 lines
5.8 KiB
LLVM
; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SICIVI %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=SICIVI %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
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; GCN-LABEL: {{^}}extract_vector_elt_v2i16:
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; GCN: s_load_dword [[VEC:s[0-9]+]]
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; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 16
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; GCN-DAG: v_mov_b32_e32 [[VELT0:v[0-9]+]], [[VEC]]
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; GCN-DAG: v_mov_b32_e32 [[VELT1:v[0-9]+]], [[ELT1]]
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; GCN-DAG: buffer_store_short [[VELT0]]
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; GCN-DAG: buffer_store_short [[VELT1]]
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define amdgpu_kernel void @extract_vector_elt_v2i16(i16 addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr) #0 {
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%vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
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%p0 = extractelement <2 x i16> %vec, i32 0
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%p1 = extractelement <2 x i16> %vec, i32 1
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%out1 = getelementptr i16, i16 addrspace(1)* %out, i32 10
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store i16 %p1, i16 addrspace(1)* %out, align 2
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store i16 %p0, i16 addrspace(1)* %out1, align 2
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ret void
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}
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; GCN-LABEL: {{^}}extract_vector_elt_v2i16_dynamic_sgpr:
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; GCN: s_load_dword [[IDX:s[0-9]+]]
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; GCN: s_load_dword [[VEC:s[0-9]+]]
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; GCN: s_lshl_b32 [[IDX_SCALED:s[0-9]+]], [[IDX]], 16
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; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], [[IDX_SCALED]]
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; GCN: v_mov_b32_e32 [[VELT1:v[0-9]+]], [[ELT1]]
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; GCN: buffer_store_short [[VELT1]]
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; GCN: ScratchSize: 0
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define amdgpu_kernel void @extract_vector_elt_v2i16_dynamic_sgpr(i16 addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, i32 %idx) #0 {
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%vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
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%elt = extractelement <2 x i16> %vec, i32 %idx
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store i16 %elt, i16 addrspace(1)* %out, align 2
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ret void
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}
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; GCN-LABEL: {{^}}extract_vector_elt_v2i16_dynamic_vgpr:
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; GCN-DAG: s_load_dword [[VEC:s[0-9]+]]
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; GCN-DAG: {{flat|buffer|global}}_load_dword [[IDX:v[0-9]+]]
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; GCN: v_lshlrev_b32_e32 [[IDX_SCALED:v[0-9]+]], 16, [[IDX]]
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; SI: v_lshr_b32_e32 [[ELT:v[0-9]+]], [[VEC]], [[IDX_SCALED]]
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; VI: v_lshrrev_b32_e64 [[ELT:v[0-9]+]], [[IDX_SCALED]], [[VEC]]
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; SI: buffer_store_short [[ELT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[ELT]]
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; GCN: ScratchSize: 0{{$}}
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define amdgpu_kernel void @extract_vector_elt_v2i16_dynamic_vgpr(i16 addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, i32 addrspace(1)* %idx.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %idx.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds i16, i16 addrspace(1)* %out, i64 %tid.ext
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%idx = load volatile i32, i32 addrspace(1)* %gep
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%vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
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%elt = extractelement <2 x i16> %vec, i32 %idx
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store i16 %elt, i16 addrspace(1)* %out.gep, align 2
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ret void
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}
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; GCN-LABEL: {{^}}extract_vector_elt_v3i16:
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; GCN: buffer_load_ushort
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; GCN: buffer_store_short
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; GCN: buffer_store_short
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define amdgpu_kernel void @extract_vector_elt_v3i16(i16 addrspace(1)* %out, <3 x i16> %foo) #0 {
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%p0 = extractelement <3 x i16> %foo, i32 0
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%p1 = extractelement <3 x i16> %foo, i32 2
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%out1 = getelementptr i16, i16 addrspace(1)* %out, i32 1
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store i16 %p1, i16 addrspace(1)* %out, align 2
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store i16 %p0, i16 addrspace(1)* %out1, align 2
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ret void
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}
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; GCN-LABEL: {{^}}extract_vector_elt_v4i16:
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; SICIVI: buffer_load_ushort
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; SICIVI: buffer_load_ushort
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; SICIVI: buffer_store_short
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; SICIVI: buffer_store_short
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; GFX9-DAG: s_load_dword [[LOAD0:s[0-9]+]], s[0:1], 0x2c
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; GFX9-DAG: s_load_dword [[LOAD1:s[0-9]+]], s[0:1], 0x30
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; GFX9-DAG: v_mov_b32_e32 [[VLOAD0:v[0-9]+]], [[LOAD0]]
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; GFX9-DAG: buffer_store_short [[VLOAD0]], off
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; GFX9-DAG: v_mov_b32_e32 [[VLOAD1:v[0-9]+]], [[LOAD1]]
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; GFX9-DAG: buffer_store_short [[VLOAD1]], off
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define amdgpu_kernel void @extract_vector_elt_v4i16(i16 addrspace(1)* %out, <4 x i16> %foo) #0 {
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%p0 = extractelement <4 x i16> %foo, i32 0
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%p1 = extractelement <4 x i16> %foo, i32 2
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%out1 = getelementptr i16, i16 addrspace(1)* %out, i32 10
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store volatile i16 %p1, i16 addrspace(1)* %out, align 2
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store volatile i16 %p0, i16 addrspace(1)* %out1, align 2
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ret void
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}
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; GCN-LABEL: {{^}}dynamic_extract_vector_elt_v3i16:
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; SICIVI: buffer_load_ushort
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; SICIVI: buffer_load_ushort
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; SICIVI: buffer_load_ushort
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; SICIVI: buffer_store_short
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; SICIVI: buffer_store_short
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; SICIVI: buffer_store_short
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; SICIVI: buffer_load_ushort
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; SICIVI: buffer_store_short
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; GFX9: buffer_load_ushort
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; GFX9: global_load_short_d16_hi
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; GFX9: global_load_short_d16 v
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; GFX9: buffer_store_dword
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; GFX9: buffer_store_dword
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; GFX9: buffer_load_ushort
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; GFX9: buffer_store_short
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define amdgpu_kernel void @dynamic_extract_vector_elt_v3i16(i16 addrspace(1)* %out, <3 x i16> %foo, i32 %idx) #0 {
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%p0 = extractelement <3 x i16> %foo, i32 %idx
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%out1 = getelementptr i16, i16 addrspace(1)* %out, i32 1
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store i16 %p0, i16 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}dynamic_extract_vector_elt_v4i16:
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; SICIVI: buffer_load_ushort
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; SICIVI: buffer_load_ushort
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; SICIVI: buffer_load_ushort
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; SICIVI: buffer_load_ushort
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; SICIVI: buffer_store_short
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; SICIVI: buffer_store_short
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; SICIVI: buffer_store_short
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; SICIVI: buffer_store_short
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; SICIVI: buffer_load_ushort
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; SICIVI: buffer_store_short
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; GFX9: s_load_dword
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; GFX9: buffer_store_dword
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; GFX9: buffer_store_dword
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; GFX9: buffer_load_ushort
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; GFX9: buffer_store_short
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define amdgpu_kernel void @dynamic_extract_vector_elt_v4i16(i16 addrspace(1)* %out, <4 x i16> %foo, i32 %idx) #0 {
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%p0 = extractelement <4 x i16> %foo, i32 %idx
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%out1 = getelementptr i16, i16 addrspace(1)* %out, i32 1
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store i16 %p0, i16 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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