forked from OSchip/llvm-project
170 lines
4.3 KiB
C++
170 lines
4.3 KiB
C++
//===-- AMDGPULowerIntrinsics.cpp -----------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Transforms/Utils/LowerMemIntrinsics.h"
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#define DEBUG_TYPE "amdgpu-lower-intrinsics"
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using namespace llvm;
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namespace {
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const unsigned MaxStaticSize = 1024;
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class AMDGPULowerIntrinsics : public ModulePass {
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private:
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bool makeLIDRangeMetadata(Function &F) const;
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public:
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static char ID;
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AMDGPULowerIntrinsics() : ModulePass(ID) {}
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bool runOnModule(Module &M) override;
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bool expandMemIntrinsicUses(Function &F);
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StringRef getPassName() const override {
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return "AMDGPU Lower Intrinsics";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<TargetTransformInfoWrapperPass>();
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}
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};
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}
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char AMDGPULowerIntrinsics::ID = 0;
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char &llvm::AMDGPULowerIntrinsicsID = AMDGPULowerIntrinsics::ID;
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INITIALIZE_PASS(AMDGPULowerIntrinsics, DEBUG_TYPE, "Lower intrinsics", false,
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false)
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// TODO: Should refine based on estimated number of accesses (e.g. does it
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// require splitting based on alignment)
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static bool shouldExpandOperationWithSize(Value *Size) {
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ConstantInt *CI = dyn_cast<ConstantInt>(Size);
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return !CI || (CI->getZExtValue() > MaxStaticSize);
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}
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bool AMDGPULowerIntrinsics::expandMemIntrinsicUses(Function &F) {
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Intrinsic::ID ID = F.getIntrinsicID();
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bool Changed = false;
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for (auto I = F.user_begin(), E = F.user_end(); I != E;) {
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Instruction *Inst = cast<Instruction>(*I);
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++I;
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switch (ID) {
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case Intrinsic::memcpy: {
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auto *Memcpy = cast<MemCpyInst>(Inst);
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if (shouldExpandOperationWithSize(Memcpy->getLength())) {
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Function *ParentFunc = Memcpy->getParent()->getParent();
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const TargetTransformInfo &TTI =
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getAnalysis<TargetTransformInfoWrapperPass>().getTTI(*ParentFunc);
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expandMemCpyAsLoop(Memcpy, TTI);
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Changed = true;
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Memcpy->eraseFromParent();
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}
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break;
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}
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case Intrinsic::memmove: {
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auto *Memmove = cast<MemMoveInst>(Inst);
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if (shouldExpandOperationWithSize(Memmove->getLength())) {
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expandMemMoveAsLoop(Memmove);
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Changed = true;
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Memmove->eraseFromParent();
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}
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break;
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}
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case Intrinsic::memset: {
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auto *Memset = cast<MemSetInst>(Inst);
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if (shouldExpandOperationWithSize(Memset->getLength())) {
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expandMemSetAsLoop(Memset);
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Changed = true;
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Memset->eraseFromParent();
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}
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break;
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}
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default:
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break;
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}
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}
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return Changed;
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}
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bool AMDGPULowerIntrinsics::makeLIDRangeMetadata(Function &F) const {
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auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
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if (!TPC)
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return false;
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const TargetMachine &TM = TPC->getTM<TargetMachine>();
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bool Changed = false;
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for (auto *U : F.users()) {
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auto *CI = dyn_cast<CallInst>(U);
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if (!CI)
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continue;
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Changed |= AMDGPUCommonSubtarget::get(TM, F).makeLIDRangeMetadata(CI);
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}
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return Changed;
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}
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bool AMDGPULowerIntrinsics::runOnModule(Module &M) {
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bool Changed = false;
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for (Function &F : M) {
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if (!F.isDeclaration())
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continue;
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switch (F.getIntrinsicID()) {
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case Intrinsic::memcpy:
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case Intrinsic::memmove:
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case Intrinsic::memset:
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if (expandMemIntrinsicUses(F))
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Changed = true;
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break;
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case Intrinsic::amdgcn_workitem_id_x:
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case Intrinsic::r600_read_tidig_x:
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case Intrinsic::amdgcn_workitem_id_y:
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case Intrinsic::r600_read_tidig_y:
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case Intrinsic::amdgcn_workitem_id_z:
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case Intrinsic::r600_read_tidig_z:
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case Intrinsic::r600_read_local_size_x:
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case Intrinsic::r600_read_local_size_y:
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case Intrinsic::r600_read_local_size_z:
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Changed |= makeLIDRangeMetadata(F);
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break;
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default:
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break;
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}
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}
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return Changed;
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}
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ModulePass *llvm::createAMDGPULowerIntrinsicsPass() {
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return new AMDGPULowerIntrinsics();
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}
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