forked from OSchip/llvm-project
395 lines
12 KiB
LLVM
395 lines
12 KiB
LLVM
; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s
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; CHECK: intarg
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; The save/restore frame is not strictly necessary here, but we would need to
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; refer to %o registers instead.
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; CHECK: save %sp, -128, %sp
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; CHECK: stb %i0, [%i4]
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; CHECK: stb %i1, [%i4]
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; CHECK: sth %i2, [%i4]
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; CHECK: st %i3, [%i4]
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; CHECK: stx %i4, [%i4]
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; CHECK: st %i5, [%i4]
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; CHECK: ld [%fp+2227], [[R:%[gilo][0-7]]]
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; CHECK: st [[R]], [%i4]
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; CHECK: ldx [%fp+2231], [[R:%[gilo][0-7]]]
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; CHECK: stx [[R]], [%i4]
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; CHECK: restore
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define void @intarg(i8 %a0, ; %i0
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i8 %a1, ; %i1
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i16 %a2, ; %i2
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i32 %a3, ; %i3
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i8* %a4, ; %i4
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i32 %a5, ; %i5
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i32 signext %a6, ; [%fp+BIAS+176]
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i8* %a7) { ; [%fp+BIAS+184]
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store i8 %a0, i8* %a4
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store i8 %a1, i8* %a4
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%p16 = bitcast i8* %a4 to i16*
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store i16 %a2, i16* %p16
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%p32 = bitcast i8* %a4 to i32*
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store i32 %a3, i32* %p32
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%pp = bitcast i8* %a4 to i8**
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store i8* %a4, i8** %pp
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store i32 %a5, i32* %p32
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store i32 %a6, i32* %p32
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store i8* %a7, i8** %pp
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ret void
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}
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; CHECK: call_intarg
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; 16 saved + 8 args.
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; CHECK: save %sp, -192, %sp
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; Sign-extend and store the full 64 bits.
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; CHECK: sra %i0, 0, [[R:%[gilo][0-7]]]
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; CHECK: stx [[R]], [%sp+2223]
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; Use %o0-%o5 for outgoing arguments
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; CHECK: or %g0, 5, %o5
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; CHECK: call intarg
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; CHECK-NOT: add %sp
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; CHECK: restore
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define void @call_intarg(i32 %i0, i8* %i1) {
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call void @intarg(i8 0, i8 1, i16 2, i32 3, i8* undef, i32 5, i32 %i0, i8* %i1)
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ret void
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}
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; CHECK: floatarg
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; CHECK: save %sp, -128, %sp
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; CHECK: fstod %f1,
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; CHECK: faddd %f2,
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; CHECK: faddd %f4,
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; CHECK: faddd %f6,
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; CHECK: ld [%fp+2307], [[F:%f[0-9]+]]
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; CHECK: fadds %f31, [[F]]
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define double @floatarg(float %a0, ; %f1
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double %a1, ; %d2
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double %a2, ; %d4
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double %a3, ; %d6
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float %a4, ; %f9
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float %a5, ; %f11
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float %a6, ; %f13
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float %a7, ; %f15
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float %a8, ; %f17
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float %a9, ; %f19
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float %a10, ; %f21
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float %a11, ; %f23
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float %a12, ; %f25
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float %a13, ; %f27
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float %a14, ; %f29
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float %a15, ; %f31
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float %a16, ; [%fp+BIAS+256] (using 8 bytes)
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double %a17) { ; [%fp+BIAS+264] (using 8 bytes)
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%d0 = fpext float %a0 to double
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%s1 = fadd double %a1, %d0
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%s2 = fadd double %a2, %s1
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%s3 = fadd double %a3, %s2
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%s16 = fadd float %a15, %a16
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%d16 = fpext float %s16 to double
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%s17 = fadd double %d16, %s3
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ret double %s17
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}
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; CHECK: call_floatarg
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; CHECK: save %sp, -272, %sp
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; Store 4 bytes, right-aligned in slot.
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; CHECK: st %f1, [%sp+2307]
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; Store 8 bytes in full slot.
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; CHECK: std %f2, [%sp+2311]
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; CHECK: fmovd %f2, %f4
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; CHECK: call floatarg
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; CHECK-NOT: add %sp
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; CHECK: restore
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define void @call_floatarg(float %f1, double %d2, float %f5, double *%p) {
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%r = call double @floatarg(float %f5, double %d2, double %d2, double %d2,
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float %f5, float %f5, float %f5, float %f5,
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float %f5, float %f5, float %f5, float %f5,
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float %f5, float %f5, float %f5, float %f5,
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float %f1, double %d2)
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store double %r, double* %p
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ret void
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}
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; CHECK: mixedarg
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; CHECK: fstod %f3
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; CHECK: faddd %f6
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; CHECK: faddd %f16
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; CHECK: ldx [%fp+2231]
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; CHECK: ldx [%fp+2247]
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define void @mixedarg(i8 %a0, ; %i0
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float %a1, ; %f3
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i16 %a2, ; %i2
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double %a3, ; %d6
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i13 %a4, ; %i4
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float %a5, ; %f11
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i64 %a6, ; [%fp+BIAS+176]
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double *%a7, ; [%fp+BIAS+184]
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double %a8, ; %d16
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i16* %a9) { ; [%fp+BIAS+200]
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%d1 = fpext float %a1 to double
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%s3 = fadd double %a3, %d1
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%s8 = fadd double %a8, %s3
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store double %s8, double* %a7
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store i16 %a2, i16* %a9
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ret void
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}
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; CHECK: call_mixedarg
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; CHECK: stx %i2, [%sp+2247]
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; CHECK: stx %i0, [%sp+2223]
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; CHECK: fmovd %f2, %f6
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; CHECK: fmovd %f2, %f16
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; CHECK: call mixedarg
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; CHECK-NOT: add %sp
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; CHECK: restore
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define void @call_mixedarg(i64 %i0, double %f2, i16* %i2) {
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call void @mixedarg(i8 undef,
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float undef,
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i16 undef,
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double %f2,
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i13 undef,
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float undef,
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i64 %i0,
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double* undef,
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double %f2,
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i16* %i2)
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ret void
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}
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; The inreg attribute is used to indicate 32-bit sized struct elements that
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; share an 8-byte slot.
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; CHECK: inreg_fi
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; CHECK: fstoi %f1
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; CHECK: srlx %i0, 32, [[R:%[gilo][0-7]]]
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; CHECK: sub [[R]],
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define i32 @inreg_fi(i32 inreg %a0, ; high bits of %i0
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float inreg %a1) { ; %f1
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%b1 = fptosi float %a1 to i32
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%rv = sub i32 %a0, %b1
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ret i32 %rv
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}
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; CHECK: call_inreg_fi
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; Allocate space for 6 arguments, even when only 2 are used.
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; CHECK: save %sp, -176, %sp
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; CHECK: sllx %i1, 32, %o0
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; CHECK: fmovs %f5, %f1
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; CHECK: call inreg_fi
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define void @call_inreg_fi(i32* %p, i32 %i1, float %f5) {
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%x = call i32 @inreg_fi(i32 %i1, float %f5)
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ret void
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}
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; CHECK: inreg_ff
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; CHECK: fsubs %f0, %f1, %f1
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define float @inreg_ff(float inreg %a0, ; %f0
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float inreg %a1) { ; %f1
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%rv = fsub float %a0, %a1
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ret float %rv
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}
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; CHECK: call_inreg_ff
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; CHECK: fmovs %f3, %f0
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; CHECK: fmovs %f5, %f1
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; CHECK: call inreg_ff
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define void @call_inreg_ff(i32* %p, float %f3, float %f5) {
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%x = call float @inreg_ff(float %f3, float %f5)
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ret void
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}
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; CHECK: inreg_if
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; CHECK: fstoi %f0
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; CHECK: sub %i0
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define i32 @inreg_if(float inreg %a0, ; %f0
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i32 inreg %a1) { ; low bits of %i0
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%b0 = fptosi float %a0 to i32
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%rv = sub i32 %a1, %b0
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ret i32 %rv
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}
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; CHECK: call_inreg_if
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; CHECK: fmovs %f3, %f0
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; CHECK: or %g0, %i2, %o0
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; CHECK: call inreg_if
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define void @call_inreg_if(i32* %p, float %f3, i32 %i2) {
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%x = call i32 @inreg_if(float %f3, i32 %i2)
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ret void
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}
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; The frontend shouldn't do this. Just pass i64 instead.
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; CHECK: inreg_ii
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; CHECK: srlx %i0, 32, [[R:%[gilo][0-7]]]
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; CHECK: sub %i0, [[R]], %i0
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define i32 @inreg_ii(i32 inreg %a0, ; high bits of %i0
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i32 inreg %a1) { ; low bits of %i0
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%rv = sub i32 %a1, %a0
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ret i32 %rv
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}
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; CHECK: call_inreg_ii
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; CHECK: srl %i2, 0, [[R2:%[gilo][0-7]]]
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; CHECK: sllx %i1, 32, [[R1:%[gilo][0-7]]]
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; CHECK: or [[R1]], [[R2]], %o0
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; CHECK: call inreg_ii
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define void @call_inreg_ii(i32* %p, i32 %i1, i32 %i2) {
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%x = call i32 @inreg_ii(i32 %i1, i32 %i2)
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ret void
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}
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; Structs up to 32 bytes in size can be returned in registers.
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; CHECK: ret_i64_pair
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; CHECK: ldx [%i2], %i0
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; CHECK: ldx [%i3], %i1
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define { i64, i64 } @ret_i64_pair(i32 %a0, i32 %a1, i64* %p, i64* %q) {
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%r1 = load i64* %p
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%rv1 = insertvalue { i64, i64 } undef, i64 %r1, 0
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store i64 0, i64* %p
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%r2 = load i64* %q
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%rv2 = insertvalue { i64, i64 } %rv1, i64 %r2, 1
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ret { i64, i64 } %rv2
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}
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; CHECK: call_ret_i64_pair
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; CHECK: call ret_i64_pair
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; CHECK: stx %o0, [%i0]
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; CHECK: stx %o1, [%i0]
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define void @call_ret_i64_pair(i64* %i0) {
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%rv = call { i64, i64 } @ret_i64_pair(i32 undef, i32 undef,
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i64* undef, i64* undef)
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%e0 = extractvalue { i64, i64 } %rv, 0
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store i64 %e0, i64* %i0
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%e1 = extractvalue { i64, i64 } %rv, 1
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store i64 %e1, i64* %i0
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ret void
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}
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; This is not a C struct, each member uses 8 bytes.
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; CHECK: ret_i32_float_pair
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; CHECK: ld [%i2], %i0
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; CHECK: ld [%i3], %f3
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define { i32, float } @ret_i32_float_pair(i32 %a0, i32 %a1,
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i32* %p, float* %q) {
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%r1 = load i32* %p
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%rv1 = insertvalue { i32, float } undef, i32 %r1, 0
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store i32 0, i32* %p
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%r2 = load float* %q
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%rv2 = insertvalue { i32, float } %rv1, float %r2, 1
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ret { i32, float } %rv2
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}
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; CHECK: call_ret_i32_float_pair
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; CHECK: call ret_i32_float_pair
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; CHECK: st %o0, [%i0]
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; CHECK: st %f3, [%i1]
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define void @call_ret_i32_float_pair(i32* %i0, float* %i1) {
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%rv = call { i32, float } @ret_i32_float_pair(i32 undef, i32 undef,
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i32* undef, float* undef)
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%e0 = extractvalue { i32, float } %rv, 0
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store i32 %e0, i32* %i0
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%e1 = extractvalue { i32, float } %rv, 1
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store float %e1, float* %i1
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ret void
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}
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; This is a C struct, each member uses 4 bytes.
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; CHECK: ret_i32_float_packed
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; CHECK: ld [%i2], [[R:%[gilo][0-7]]]
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; CHECK: sllx [[R]], 32, %i0
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; CHECK: ld [%i3], %f1
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define inreg { i32, float } @ret_i32_float_packed(i32 %a0, i32 %a1,
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i32* %p, float* %q) {
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%r1 = load i32* %p
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%rv1 = insertvalue { i32, float } undef, i32 %r1, 0
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store i32 0, i32* %p
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%r2 = load float* %q
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%rv2 = insertvalue { i32, float } %rv1, float %r2, 1
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ret { i32, float } %rv2
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}
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; CHECK: call_ret_i32_float_packed
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; CHECK: call ret_i32_float_packed
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; CHECK: srlx %o0, 32, [[R:%[gilo][0-7]]]
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; CHECK: st [[R]], [%i0]
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; CHECK: st %f1, [%i1]
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define void @call_ret_i32_float_packed(i32* %i0, float* %i1) {
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%rv = call { i32, float } @ret_i32_float_packed(i32 undef, i32 undef,
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i32* undef, float* undef)
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%e0 = extractvalue { i32, float } %rv, 0
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store i32 %e0, i32* %i0
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%e1 = extractvalue { i32, float } %rv, 1
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store float %e1, float* %i1
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ret void
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}
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; The C frontend should use i64 to return { i32, i32 } structs, but verify that
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; we don't miscompile thi case where both struct elements are placed in %i0.
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; CHECK: ret_i32_packed
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; CHECK: ld [%i2], [[R1:%[gilo][0-7]]]
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; CHECK: ld [%i3], [[R2:%[gilo][0-7]]]
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; CHECK: sllx [[R2]], 32, [[R3:%[gilo][0-7]]]
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; CHECK: or [[R3]], [[R1]], %i0
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define inreg { i32, i32 } @ret_i32_packed(i32 %a0, i32 %a1,
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i32* %p, i32* %q) {
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%r1 = load i32* %p
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%rv1 = insertvalue { i32, i32 } undef, i32 %r1, 1
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store i32 0, i32* %p
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%r2 = load i32* %q
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%rv2 = insertvalue { i32, i32 } %rv1, i32 %r2, 0
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ret { i32, i32 } %rv2
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}
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; CHECK: call_ret_i32_packed
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; CHECK: call ret_i32_packed
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; CHECK: srlx %o0, 32, [[R:%[gilo][0-7]]]
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; CHECK: st [[R]], [%i0]
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; CHECK: st %o0, [%i1]
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define void @call_ret_i32_packed(i32* %i0, i32* %i1) {
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%rv = call { i32, i32 } @ret_i32_packed(i32 undef, i32 undef,
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i32* undef, i32* undef)
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%e0 = extractvalue { i32, i32 } %rv, 0
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store i32 %e0, i32* %i0
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%e1 = extractvalue { i32, i32 } %rv, 1
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store i32 %e1, i32* %i1
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ret void
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}
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; The return value must be sign-extended to 64 bits.
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; CHECK: ret_sext
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; CHECK: sra %i0, 0, %i0
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define signext i32 @ret_sext(i32 %a0) {
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ret i32 %a0
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}
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; CHECK: ret_zext
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; CHECK: srl %i0, 0, %i0
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define zeroext i32 @ret_zext(i32 %a0) {
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ret i32 %a0
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}
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; CHECK: ret_nosext
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; CHECK-NOT: sra
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define signext i32 @ret_nosext(i32 signext %a0) {
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ret i32 %a0
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}
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; CHECK: ret_nozext
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; CHECK-NOT: srl
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define signext i32 @ret_nozext(i32 signext %a0) {
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ret i32 %a0
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}
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; CHECK-LABEL: test_register_directive
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; CHECK: .register %g2, #scratch
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; CHECK: .register %g3, #scratch
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; CHECK: .register %g6, #ignore
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; CHECK: .register %g7, #ignore
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; CHECK: add %i0, 2, %g2
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; CHECK: add %i0, 3, %g3
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define i32 @test_register_directive(i32 %i0) {
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entry:
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%0 = add nsw i32 %i0, 2
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%1 = add nsw i32 %i0, 3
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tail call void asm sideeffect "", "r,r,~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6},~{o7},~{g1},~{g4},~{g5},~{g6},~{g7}"(i32 %0, i32 %1)
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%2 = add nsw i32 %0, %1
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ret i32 %2
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}
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