forked from OSchip/llvm-project
954 lines
32 KiB
C++
954 lines
32 KiB
C++
//===-- X86/Printer.cpp - Convert X86 LLVM code to Intel assembly ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to Intel-format assembly language. This
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// printer is the output mechanism used by `llc' and `lli -print-machineinstrs'
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// on X86.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Module.h"
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#include "llvm/Assembly/Writer.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Mangler.h"
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#include "Support/Statistic.h"
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#include "Support/StringExtras.h"
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#include "Support/CommandLine.h"
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using namespace llvm;
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namespace {
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Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
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// FIXME: This should be automatically picked up by autoconf from the C
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// frontend
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cl::opt<bool> EmitCygwin("enable-cygwin-compatible-output", cl::Hidden,
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cl::desc("Emit X86 assembly code suitable for consumption by cygwin"));
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struct Printer : public MachineFunctionPass {
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/// Output stream on which we're printing assembly code.
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///
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std::ostream &O;
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/// Target machine description which we query for reg. names, data
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/// layout, etc.
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///
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TargetMachine &TM;
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/// Name-mangler for global names.
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///
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Mangler *Mang;
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Printer(std::ostream &o, TargetMachine &tm) : O(o), TM(tm) { }
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/// We name each basic block in a Function with a unique number, so
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/// that we can consistently refer to them later. This is cleared
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/// at the beginning of each call to runOnMachineFunction().
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///
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typedef std::map<const Value *, unsigned> ValueMapTy;
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ValueMapTy NumberForBB;
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/// Cache of mangled name for current function. This is
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/// recalculated at the beginning of each call to
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/// runOnMachineFunction().
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///
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std::string CurrentFnName;
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virtual const char *getPassName() const {
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return "X86 Assembly Printer";
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}
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void checkImplUses (const TargetInstrDescriptor &Desc);
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void printMachineInstruction(const MachineInstr *MI);
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void printOp(const MachineOperand &MO,
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bool elideOffsetKeyword = false);
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void printMemReference(const MachineInstr *MI, unsigned Op);
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void printConstantPool(MachineConstantPool *MCP);
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bool runOnMachineFunction(MachineFunction &F);
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bool doInitialization(Module &M);
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bool doFinalization(Module &M);
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void emitGlobalConstant(const Constant* CV);
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void emitConstantValueOnly(const Constant *CV);
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};
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} // end of anonymous namespace
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/// createX86CodePrinterPass - Returns a pass that prints the X86
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/// assembly code for a MachineFunction to the given output stream,
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/// using the given target machine description. This should work
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/// regardless of whether the function is in SSA form.
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///
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FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){
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return new Printer(o, tm);
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}
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/// toOctal - Convert the low order bits of X into an octal digit.
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///
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static inline char toOctal(int X) {
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return (X&7)+'0';
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}
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/// getAsCString - Return the specified array as a C compatible
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/// string, only if the predicate isStringCompatible is true.
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///
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static void printAsCString(std::ostream &O, const ConstantArray *CVA) {
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assert(CVA->isString() && "Array is not string compatible!");
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O << "\"";
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for (unsigned i = 0; i != CVA->getNumOperands(); ++i) {
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unsigned char C = cast<ConstantInt>(CVA->getOperand(i))->getRawValue();
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if (C == '"') {
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O << "\\\"";
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} else if (C == '\\') {
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O << "\\\\";
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} else if (isprint(C)) {
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O << C;
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} else {
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switch(C) {
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case '\b': O << "\\b"; break;
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case '\f': O << "\\f"; break;
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case '\n': O << "\\n"; break;
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case '\r': O << "\\r"; break;
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case '\t': O << "\\t"; break;
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default:
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O << '\\';
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O << toOctal(C >> 6);
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O << toOctal(C >> 3);
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O << toOctal(C >> 0);
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break;
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}
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}
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}
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O << "\"";
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}
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// Print out the specified constant, without a storage class. Only the
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// constants valid in constant expressions can occur here.
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void Printer::emitConstantValueOnly(const Constant *CV) {
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if (CV->isNullValue())
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O << "0";
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else if (const ConstantBool *CB = dyn_cast<ConstantBool>(CV)) {
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assert(CB == ConstantBool::True);
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O << "1";
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} else if (const ConstantSInt *CI = dyn_cast<ConstantSInt>(CV))
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if (((CI->getValue() << 32) >> 32) == CI->getValue())
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O << CI->getValue();
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else
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O << (unsigned long long)CI->getValue();
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else if (const ConstantUInt *CI = dyn_cast<ConstantUInt>(CV))
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O << CI->getValue();
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else if (const ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(CV))
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// This is a constant address for a global variable or function. Use the
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// name of the variable or function as the address value.
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O << Mang->getValueName(CPR->getValue());
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else if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV)) {
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const TargetData &TD = TM.getTargetData();
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switch(CE->getOpcode()) {
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case Instruction::GetElementPtr: {
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// generate a symbolic expression for the byte address
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const Constant *ptrVal = CE->getOperand(0);
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std::vector<Value*> idxVec(CE->op_begin()+1, CE->op_end());
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if (unsigned Offset = TD.getIndexedOffset(ptrVal->getType(), idxVec)) {
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O << "(";
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emitConstantValueOnly(ptrVal);
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O << ") + " << Offset;
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} else {
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emitConstantValueOnly(ptrVal);
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}
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break;
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}
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case Instruction::Cast: {
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// Support only non-converting or widening casts for now, that is, ones
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// that do not involve a change in value. This assertion is really gross,
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// and may not even be a complete check.
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Constant *Op = CE->getOperand(0);
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const Type *OpTy = Op->getType(), *Ty = CE->getType();
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// Remember, kids, pointers on x86 can be losslessly converted back and
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// forth into 32-bit or wider integers, regardless of signedness. :-P
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assert(((isa<PointerType>(OpTy)
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&& (Ty == Type::LongTy || Ty == Type::ULongTy
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|| Ty == Type::IntTy || Ty == Type::UIntTy))
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|| (isa<PointerType>(Ty)
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&& (OpTy == Type::LongTy || OpTy == Type::ULongTy
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|| OpTy == Type::IntTy || OpTy == Type::UIntTy))
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|| (((TD.getTypeSize(Ty) >= TD.getTypeSize(OpTy))
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&& OpTy->isLosslesslyConvertibleTo(Ty))))
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&& "FIXME: Don't yet support this kind of constant cast expr");
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O << "(";
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emitConstantValueOnly(Op);
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O << ")";
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break;
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}
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case Instruction::Add:
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O << "(";
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emitConstantValueOnly(CE->getOperand(0));
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O << ") + (";
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emitConstantValueOnly(CE->getOperand(1));
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O << ")";
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break;
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default:
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assert(0 && "Unsupported operator!");
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}
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} else {
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assert(0 && "Unknown constant value!");
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}
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}
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// Print a constant value or values, with the appropriate storage class as a
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// prefix.
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void Printer::emitGlobalConstant(const Constant *CV) {
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const TargetData &TD = TM.getTargetData();
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if (CV->isNullValue()) {
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O << "\t.zero\t " << TD.getTypeSize(CV->getType()) << "\n";
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return;
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} else if (const ConstantArray *CVA = dyn_cast<ConstantArray>(CV)) {
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if (CVA->isString()) {
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O << "\t.ascii\t";
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printAsCString(O, CVA);
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O << "\n";
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} else { // Not a string. Print the values in successive locations
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const std::vector<Use> &constValues = CVA->getValues();
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for (unsigned i=0; i < constValues.size(); i++)
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emitGlobalConstant(cast<Constant>(constValues[i].get()));
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}
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return;
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} else if (const ConstantStruct *CVS = dyn_cast<ConstantStruct>(CV)) {
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// Print the fields in successive locations. Pad to align if needed!
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const StructLayout *cvsLayout = TD.getStructLayout(CVS->getType());
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const std::vector<Use>& constValues = CVS->getValues();
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unsigned sizeSoFar = 0;
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for (unsigned i=0, N = constValues.size(); i < N; i++) {
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const Constant* field = cast<Constant>(constValues[i].get());
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// Check if padding is needed and insert one or more 0s.
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unsigned fieldSize = TD.getTypeSize(field->getType());
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unsigned padSize = ((i == N-1? cvsLayout->StructSize
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: cvsLayout->MemberOffsets[i+1])
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- cvsLayout->MemberOffsets[i]) - fieldSize;
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sizeSoFar += fieldSize + padSize;
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// Now print the actual field value
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emitGlobalConstant(field);
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// Insert the field padding unless it's zero bytes...
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if (padSize)
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O << "\t.zero\t " << padSize << "\n";
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}
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assert(sizeSoFar == cvsLayout->StructSize &&
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"Layout of constant struct may be incorrect!");
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return;
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} else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
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// FP Constants are printed as integer constants to avoid losing
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// precision...
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double Val = CFP->getValue();
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switch (CFP->getType()->getPrimitiveID()) {
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default: assert(0 && "Unknown floating point type!");
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case Type::FloatTyID: {
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union FU { // Abide by C TBAA rules
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float FVal;
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unsigned UVal;
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} U;
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U.FVal = Val;
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O << ".long\t" << U.UVal << "\t# float " << Val << "\n";
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return;
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}
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case Type::DoubleTyID: {
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union DU { // Abide by C TBAA rules
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double FVal;
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uint64_t UVal;
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} U;
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U.FVal = Val;
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O << ".quad\t" << U.UVal << "\t# double " << Val << "\n";
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return;
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}
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}
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}
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const Type *type = CV->getType();
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O << "\t";
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switch (type->getPrimitiveID()) {
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case Type::BoolTyID: case Type::UByteTyID: case Type::SByteTyID:
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O << ".byte";
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break;
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case Type::UShortTyID: case Type::ShortTyID:
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O << ".word";
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break;
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case Type::FloatTyID: case Type::PointerTyID:
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case Type::UIntTyID: case Type::IntTyID:
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O << ".long";
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break;
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case Type::DoubleTyID:
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case Type::ULongTyID: case Type::LongTyID:
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O << ".quad";
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break;
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default:
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assert (0 && "Can't handle printing this type of thing");
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break;
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}
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O << "\t";
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emitConstantValueOnly(CV);
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O << "\n";
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}
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/// printConstantPool - Print to the current output stream assembly
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/// representations of the constants in the constant pool MCP. This is
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/// used to print out constants which have been "spilled to memory" by
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/// the code generator.
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///
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void Printer::printConstantPool(MachineConstantPool *MCP) {
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const std::vector<Constant*> &CP = MCP->getConstants();
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const TargetData &TD = TM.getTargetData();
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if (CP.empty()) return;
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for (unsigned i = 0, e = CP.size(); i != e; ++i) {
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O << "\t.section .rodata\n";
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O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType())
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<< "\n";
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O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t#"
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<< *CP[i] << "\n";
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emitGlobalConstant(CP[i]);
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}
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}
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/// runOnMachineFunction - This uses the printMachineInstruction()
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/// method to print assembly for each instruction.
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///
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bool Printer::runOnMachineFunction(MachineFunction &MF) {
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// BBNumber is used here so that a given Printer will never give two
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// BBs the same name. (If you have a better way, please let me know!)
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static unsigned BBNumber = 0;
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O << "\n\n";
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// What's my mangled name?
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CurrentFnName = Mang->getValueName(MF.getFunction());
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// Print out constants referenced by the function
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printConstantPool(MF.getConstantPool());
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// Print out labels for the function.
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O << "\t.text\n";
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O << "\t.align 16\n";
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O << "\t.globl\t" << CurrentFnName << "\n";
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if (!EmitCygwin)
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O << "\t.type\t" << CurrentFnName << ", @function\n";
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O << CurrentFnName << ":\n";
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// Number each basic block so that we can consistently refer to them
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// in PC-relative references.
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NumberForBB.clear();
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for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
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I != E; ++I) {
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NumberForBB[I->getBasicBlock()] = BBNumber++;
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}
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// Print out code for the function.
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for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
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I != E; ++I) {
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// Print a label for the basic block.
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O << ".LBB" << NumberForBB[I->getBasicBlock()] << ":\t# "
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<< I->getBasicBlock()->getName() << "\n";
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for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
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II != E; ++II) {
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// Print the assembly for the instruction.
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O << "\t";
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printMachineInstruction(II);
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}
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}
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// We didn't modify anything.
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return false;
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}
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static bool isScale(const MachineOperand &MO) {
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return MO.isImmediate() &&
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(MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
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MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
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}
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static bool isMem(const MachineInstr *MI, unsigned Op) {
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if (MI->getOperand(Op).isFrameIndex()) return true;
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if (MI->getOperand(Op).isConstantPoolIndex()) return true;
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return Op+4 <= MI->getNumOperands() &&
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MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) &&
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MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
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}
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void Printer::printOp(const MachineOperand &MO,
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bool elideOffsetKeyword /* = false */) {
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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switch (MO.getType()) {
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case MachineOperand::MO_VirtualRegister:
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if (Value *V = MO.getVRegValueOrNull()) {
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O << "<" << V->getName() << ">";
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return;
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}
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// FALLTHROUGH
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case MachineOperand::MO_MachineRegister:
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if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
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// Bug Workaround: See note in Printer::doInitialization about %.
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O << "%" << RI.get(MO.getReg()).Name;
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else
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O << "%reg" << MO.getReg();
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return;
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case MachineOperand::MO_SignExtendedImmed:
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case MachineOperand::MO_UnextendedImmed:
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O << (int)MO.getImmedValue();
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return;
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case MachineOperand::MO_PCRelativeDisp: {
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ValueMapTy::const_iterator i = NumberForBB.find(MO.getVRegValue());
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assert (i != NumberForBB.end()
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&& "Could not find a BB in the NumberForBB map!");
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O << ".LBB" << i->second << " # PC rel: " << MO.getVRegValue()->getName();
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return;
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}
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case MachineOperand::MO_GlobalAddress:
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if (!elideOffsetKeyword)
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O << "OFFSET ";
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O << Mang->getValueName(MO.getGlobal());
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return;
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case MachineOperand::MO_ExternalSymbol:
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O << MO.getSymbolName();
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return;
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default:
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O << "<unknown operand type>"; return;
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}
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}
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static const char* const sizePtr(const TargetInstrDescriptor &Desc) {
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switch (Desc.TSFlags & X86II::MemMask) {
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default: assert(0 && "Unknown arg size!");
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case X86II::Mem8: return "BYTE PTR";
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case X86II::Mem16: return "WORD PTR";
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case X86II::Mem32: return "DWORD PTR";
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case X86II::Mem64: return "QWORD PTR";
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case X86II::Mem80: return "XWORD PTR";
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}
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}
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void Printer::printMemReference(const MachineInstr *MI, unsigned Op) {
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assert(isMem(MI, Op) && "Invalid memory reference!");
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if (MI->getOperand(Op).isFrameIndex()) {
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O << "[frame slot #" << MI->getOperand(Op).getFrameIndex();
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if (MI->getOperand(Op+3).getImmedValue())
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O << " + " << MI->getOperand(Op+3).getImmedValue();
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O << "]";
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return;
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} else if (MI->getOperand(Op).isConstantPoolIndex()) {
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O << "[.CPI" << CurrentFnName << "_"
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<< MI->getOperand(Op).getConstantPoolIndex();
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if (MI->getOperand(Op+3).getImmedValue())
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O << " + " << MI->getOperand(Op+3).getImmedValue();
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O << "]";
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return;
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}
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const MachineOperand &BaseReg = MI->getOperand(Op);
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int ScaleVal = MI->getOperand(Op+1).getImmedValue();
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const MachineOperand &IndexReg = MI->getOperand(Op+2);
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int DispVal = MI->getOperand(Op+3).getImmedValue();
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O << "[";
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bool NeedPlus = false;
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if (BaseReg.getReg()) {
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printOp(BaseReg);
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NeedPlus = true;
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}
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if (IndexReg.getReg()) {
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if (NeedPlus) O << " + ";
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if (ScaleVal != 1)
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O << ScaleVal << "*";
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printOp(IndexReg);
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NeedPlus = true;
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}
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if (DispVal) {
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if (NeedPlus)
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if (DispVal > 0)
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|
O << " + ";
|
|
else {
|
|
O << " - ";
|
|
DispVal = -DispVal;
|
|
}
|
|
O << DispVal;
|
|
}
|
|
O << "]";
|
|
}
|
|
|
|
/// checkImplUses - Emit the implicit-use registers for the
|
|
/// instruction described by DESC, if its PrintImplUses flag is set.
|
|
///
|
|
void Printer::checkImplUses (const TargetInstrDescriptor &Desc) {
|
|
const MRegisterInfo &RI = *TM.getRegisterInfo();
|
|
if (Desc.TSFlags & X86II::PrintImplUses) {
|
|
for (const unsigned *p = Desc.ImplicitUses; *p; ++p) {
|
|
// Bug Workaround: See note in Printer::doInitialization about %.
|
|
O << ", %" << RI.get(*p).Name;
|
|
}
|
|
}
|
|
}
|
|
|
|
/// printMachineInstruction -- Print out a single X86 LLVM instruction
|
|
/// MI in Intel syntax to the current output stream.
|
|
///
|
|
void Printer::printMachineInstruction(const MachineInstr *MI) {
|
|
unsigned Opcode = MI->getOpcode();
|
|
const TargetInstrInfo &TII = TM.getInstrInfo();
|
|
const TargetInstrDescriptor &Desc = TII.get(Opcode);
|
|
|
|
++EmittedInsts;
|
|
switch (Desc.TSFlags & X86II::FormMask) {
|
|
case X86II::Pseudo:
|
|
// Print pseudo-instructions as comments; either they should have been
|
|
// turned into real instructions by now, or they don't need to be
|
|
// seen by the assembler (e.g., IMPLICIT_USEs.)
|
|
O << "# ";
|
|
if (Opcode == X86::PHI) {
|
|
printOp(MI->getOperand(0));
|
|
O << " = phi ";
|
|
for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
|
|
if (i != 1) O << ", ";
|
|
O << "[";
|
|
printOp(MI->getOperand(i));
|
|
O << ", ";
|
|
printOp(MI->getOperand(i+1));
|
|
O << "]";
|
|
}
|
|
} else {
|
|
unsigned i = 0;
|
|
if (MI->getNumOperands() && MI->getOperand(0).isDef()) {
|
|
printOp(MI->getOperand(0));
|
|
O << " = ";
|
|
++i;
|
|
}
|
|
O << TII.getName(MI->getOpcode());
|
|
|
|
for (unsigned e = MI->getNumOperands(); i != e; ++i) {
|
|
O << " ";
|
|
if (MI->getOperand(i).isDef()) O << "*";
|
|
printOp(MI->getOperand(i));
|
|
if (MI->getOperand(i).isDef()) O << "*";
|
|
}
|
|
}
|
|
O << "\n";
|
|
return;
|
|
|
|
case X86II::RawFrm:
|
|
// The accepted forms of Raw instructions are:
|
|
// 1. nop - No operand required
|
|
// 2. jmp foo - PC relative displacement operand
|
|
// 3. call bar - GlobalAddress Operand or External Symbol Operand
|
|
//
|
|
assert(MI->getNumOperands() == 0 ||
|
|
(MI->getNumOperands() == 1 &&
|
|
(MI->getOperand(0).isPCRelativeDisp() ||
|
|
MI->getOperand(0).isGlobalAddress() ||
|
|
MI->getOperand(0).isExternalSymbol())) &&
|
|
"Illegal raw instruction!");
|
|
O << TII.getName(MI->getOpcode()) << " ";
|
|
|
|
if (MI->getNumOperands() == 1) {
|
|
printOp(MI->getOperand(0), true); // Don't print "OFFSET"...
|
|
}
|
|
O << "\n";
|
|
return;
|
|
|
|
case X86II::AddRegFrm: {
|
|
// There are currently two forms of acceptable AddRegFrm instructions.
|
|
// Either the instruction JUST takes a single register (like inc, dec, etc),
|
|
// or it takes a register and an immediate of the same size as the register
|
|
// (move immediate f.e.). Note that this immediate value might be stored as
|
|
// an LLVM value, to represent, for example, loading the address of a global
|
|
// into a register. The initial register might be duplicated if this is a
|
|
// M_2_ADDR_REG instruction
|
|
//
|
|
assert(MI->getOperand(0).isRegister() &&
|
|
(MI->getNumOperands() == 1 ||
|
|
(MI->getNumOperands() == 2 &&
|
|
(MI->getOperand(1).getVRegValueOrNull() ||
|
|
MI->getOperand(1).isImmediate() ||
|
|
MI->getOperand(1).isRegister() ||
|
|
MI->getOperand(1).isGlobalAddress() ||
|
|
MI->getOperand(1).isExternalSymbol()))) &&
|
|
"Illegal form for AddRegFrm instruction!");
|
|
|
|
unsigned Reg = MI->getOperand(0).getReg();
|
|
|
|
O << TII.getName(MI->getOpcode()) << " ";
|
|
printOp(MI->getOperand(0));
|
|
if (MI->getNumOperands() == 2 &&
|
|
(!MI->getOperand(1).isRegister() ||
|
|
MI->getOperand(1).getVRegValueOrNull() ||
|
|
MI->getOperand(1).isGlobalAddress() ||
|
|
MI->getOperand(1).isExternalSymbol())) {
|
|
O << ", ";
|
|
printOp(MI->getOperand(1));
|
|
}
|
|
checkImplUses(Desc);
|
|
O << "\n";
|
|
return;
|
|
}
|
|
case X86II::MRMDestReg: {
|
|
// There are three forms of MRMDestReg instructions, those with 2
|
|
// or 3 operands:
|
|
//
|
|
// 2 Operands: this is for things like mov that do not read a
|
|
// second input.
|
|
//
|
|
// 2 Operands: two address instructions which def&use the first
|
|
// argument and use the second as input.
|
|
//
|
|
// 3 Operands: in this form, two address instructions are the same
|
|
// as in 2 but have a constant argument as well.
|
|
//
|
|
bool isTwoAddr = TII.isTwoAddrInstr(Opcode);
|
|
assert(MI->getOperand(0).isRegister() &&
|
|
(MI->getNumOperands() == 2 ||
|
|
(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate()))
|
|
&& "Bad format for MRMDestReg!");
|
|
|
|
O << TII.getName(MI->getOpcode()) << " ";
|
|
printOp(MI->getOperand(0));
|
|
O << ", ";
|
|
printOp(MI->getOperand(1));
|
|
if (MI->getNumOperands() == 3) {
|
|
O << ", ";
|
|
printOp(MI->getOperand(2));
|
|
}
|
|
O << "\n";
|
|
return;
|
|
}
|
|
|
|
case X86II::MRMDestMem: {
|
|
// These instructions are the same as MRMDestReg, but instead of having a
|
|
// register reference for the mod/rm field, it's a memory reference.
|
|
//
|
|
assert(isMem(MI, 0) &&
|
|
(MI->getNumOperands() == 4+1 ||
|
|
(MI->getNumOperands() == 4+2 && MI->getOperand(5).isImmediate()))
|
|
&& "Bad format for MRMDestMem!");
|
|
|
|
O << TII.getName(MI->getOpcode()) << " " << sizePtr(Desc) << " ";
|
|
printMemReference(MI, 0);
|
|
O << ", ";
|
|
printOp(MI->getOperand(4));
|
|
if (MI->getNumOperands() == 4+2) {
|
|
O << ", ";
|
|
printOp(MI->getOperand(5));
|
|
}
|
|
O << "\n";
|
|
return;
|
|
}
|
|
|
|
case X86II::MRMSrcReg: {
|
|
// There are three forms that are acceptable for MRMSrcReg
|
|
// instructions, those with 2 or 3 operands:
|
|
//
|
|
// 2 Operands: this is for things like mov that do not read a
|
|
// second input.
|
|
//
|
|
// 2 Operands: in this form, the last register is the ModR/M
|
|
// input. The first operand is a def&use. This is for things
|
|
// like: add r32, r/m32
|
|
//
|
|
// 3 Operands: in this form, we can have 'INST R1, R2, imm', which is used
|
|
// for instructions like the IMULrri instructions.
|
|
//
|
|
//
|
|
assert(MI->getOperand(0).isRegister() &&
|
|
MI->getOperand(1).isRegister() &&
|
|
(MI->getNumOperands() == 2 ||
|
|
(MI->getNumOperands() == 3 &&
|
|
(MI->getOperand(2).isImmediate())))
|
|
&& "Bad format for MRMSrcReg!");
|
|
|
|
O << TII.getName(MI->getOpcode()) << " ";
|
|
printOp(MI->getOperand(0));
|
|
O << ", ";
|
|
printOp(MI->getOperand(1));
|
|
if (MI->getNumOperands() == 3) {
|
|
O << ", ";
|
|
printOp(MI->getOperand(2));
|
|
}
|
|
O << "\n";
|
|
return;
|
|
}
|
|
|
|
case X86II::MRMSrcMem: {
|
|
// These instructions are the same as MRMSrcReg, but instead of having a
|
|
// register reference for the mod/rm field, it's a memory reference.
|
|
//
|
|
assert(MI->getOperand(0).isRegister() &&
|
|
(MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
|
|
(MI->getNumOperands() == 2+4 && MI->getOperand(5).isImmediate() && isMem(MI, 1))
|
|
&& "Bad format for MRMSrcMem!");
|
|
O << TII.getName(MI->getOpcode()) << " ";
|
|
printOp(MI->getOperand(0));
|
|
O << ", " << sizePtr(Desc) << " ";
|
|
printMemReference(MI, 1);
|
|
if (MI->getNumOperands() == 2+4) {
|
|
O << ", ";
|
|
printOp(MI->getOperand(5));
|
|
}
|
|
O << "\n";
|
|
return;
|
|
}
|
|
|
|
case X86II::MRM0r: case X86II::MRM1r:
|
|
case X86II::MRM2r: case X86II::MRM3r:
|
|
case X86II::MRM4r: case X86II::MRM5r:
|
|
case X86II::MRM6r: case X86II::MRM7r: {
|
|
// In this form, the following are valid formats:
|
|
// 1. sete r
|
|
// 2. cmp reg, immediate
|
|
// 2. shl rdest, rinput <implicit CL or 1>
|
|
// 3. sbb rdest, rinput, immediate [rdest = rinput]
|
|
//
|
|
assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
|
|
MI->getOperand(0).isRegister() && "Bad MRMSxR format!");
|
|
assert((MI->getNumOperands() != 2 ||
|
|
MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&&
|
|
"Bad MRMSxR format!");
|
|
assert((MI->getNumOperands() < 3 ||
|
|
(MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) &&
|
|
"Bad MRMSxR format!");
|
|
|
|
if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() &&
|
|
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
|
|
O << "**";
|
|
|
|
O << TII.getName(MI->getOpcode()) << " ";
|
|
printOp(MI->getOperand(0));
|
|
if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) {
|
|
O << ", ";
|
|
printOp(MI->getOperand(MI->getNumOperands()-1));
|
|
}
|
|
checkImplUses(Desc);
|
|
O << "\n";
|
|
|
|
return;
|
|
}
|
|
|
|
case X86II::MRM0m: case X86II::MRM1m:
|
|
case X86II::MRM2m: case X86II::MRM3m:
|
|
case X86II::MRM4m: case X86II::MRM5m:
|
|
case X86II::MRM6m: case X86II::MRM7m: {
|
|
// In this form, the following are valid formats:
|
|
// 1. sete [m]
|
|
// 2. cmp [m], immediate
|
|
// 2. shl [m], rinput <implicit CL or 1>
|
|
// 3. sbb [m], immediate
|
|
//
|
|
assert(MI->getNumOperands() >= 4 && MI->getNumOperands() <= 5 &&
|
|
isMem(MI, 0) && "Bad MRMSxM format!");
|
|
assert((MI->getNumOperands() != 5 ||
|
|
(MI->getOperand(4).isImmediate() ||
|
|
MI->getOperand(4).isGlobalAddress())) &&
|
|
"Bad MRMSxM format!");
|
|
|
|
const MachineOperand &Op3 = MI->getOperand(3);
|
|
|
|
// Bug: The 80-bit FP store-pop instruction "fstp XWORD PTR [...]"
|
|
// is misassembled by gas in intel_syntax mode as its 32-bit
|
|
// equivalent "fstp DWORD PTR [...]". Workaround: Output the raw
|
|
// opcode bytes instead of the instruction.
|
|
if (MI->getOpcode() == X86::FSTP80m) {
|
|
if ((MI->getOperand(0).getReg() == X86::ESP)
|
|
&& (MI->getOperand(1).getImmedValue() == 1)) {
|
|
if (Op3.isImmediate() &&
|
|
Op3.getImmedValue() >= -128 && Op3.getImmedValue() <= 127) {
|
|
// 1 byte disp.
|
|
O << ".byte 0xdb, 0x7c, 0x24, 0x" << std::hex
|
|
<< ((unsigned)Op3.getImmedValue() & 255) << std::dec << "\t# ";
|
|
} else {
|
|
O << ".byte 0xdb, 0xbc, 0x24\n\t";
|
|
O << ".long ";
|
|
printOp(Op3);
|
|
O << "\t# ";
|
|
}
|
|
}
|
|
}
|
|
|
|
// Bug: The 80-bit FP load instruction "fld XWORD PTR [...]" is
|
|
// misassembled by gas in intel_syntax mode as its 32-bit
|
|
// equivalent "fld DWORD PTR [...]". Workaround: Output the raw
|
|
// opcode bytes instead of the instruction.
|
|
if (MI->getOpcode() == X86::FLD80m &&
|
|
MI->getOperand(0).getReg() == X86::ESP &&
|
|
MI->getOperand(1).getImmedValue() == 1) {
|
|
if (Op3.isImmediate() && Op3.getImmedValue() >= -128 &&
|
|
Op3.getImmedValue() <= 127) { // 1 byte displacement
|
|
O << ".byte 0xdb, 0x6c, 0x24, 0x" << std::hex
|
|
<< ((unsigned)Op3.getImmedValue() & 255) << std::dec << "\t# ";
|
|
} else {
|
|
O << ".byte 0xdb, 0xac, 0x24\n\t";
|
|
O << ".long ";
|
|
printOp(Op3);
|
|
O << "\t# ";
|
|
}
|
|
}
|
|
|
|
// Bug: gas intel_syntax mode treats "fild QWORD PTR [...]" as an
|
|
// invalid opcode, saying "64 bit operations are only supported in
|
|
// 64 bit modes." libopcodes disassembles it as "fild DWORD PTR
|
|
// [...]", which is wrong. Workaround: Output the raw opcode bytes
|
|
// instead of the instruction.
|
|
if (MI->getOpcode() == X86::FILD64m &&
|
|
MI->getOperand(0).getReg() == X86::ESP &&
|
|
MI->getOperand(1).getImmedValue() == 1) {
|
|
if (Op3.isImmediate() && Op3.getImmedValue() >= -128 &&
|
|
Op3.getImmedValue() <= 127) { // 1 byte displacement
|
|
O << ".byte 0xdf, 0x6c, 0x24, 0x" << std::hex
|
|
<< ((unsigned)Op3.getImmedValue() & 255) << std::dec << "\t# ";
|
|
} else {
|
|
O << ".byte 0xdf, 0xac, 0x24\n\t";
|
|
O << ".long ";
|
|
printOp(Op3);
|
|
O << std::dec << "\t# ";
|
|
}
|
|
}
|
|
|
|
// Bug: gas intel_syntax mode treats "fistp QWORD PTR [...]" as
|
|
// an invalid opcode, saying "64 bit operations are only
|
|
// supported in 64 bit modes." libopcodes disassembles it as
|
|
// "fistpll DWORD PTR [...]", which is wrong. Workaround: Output
|
|
// "fistpll DWORD PTR " instead, which is what libopcodes is
|
|
// expecting to see.
|
|
if (MI->getOpcode() == X86::FISTP64m) {
|
|
O << "fistpll DWORD PTR ";
|
|
printMemReference(MI, 0);
|
|
if (MI->getNumOperands() == 5) {
|
|
O << ", ";
|
|
printOp(MI->getOperand(4));
|
|
}
|
|
O << "\t# ";
|
|
}
|
|
|
|
O << TII.getName(MI->getOpcode()) << " ";
|
|
O << sizePtr(Desc) << " ";
|
|
printMemReference(MI, 0);
|
|
if (MI->getNumOperands() == 5) {
|
|
O << ", ";
|
|
printOp(MI->getOperand(4));
|
|
}
|
|
O << "\n";
|
|
return;
|
|
}
|
|
|
|
default:
|
|
O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break;
|
|
}
|
|
}
|
|
|
|
bool Printer::doInitialization(Module &M) {
|
|
// Tell gas we are outputting Intel syntax (not AT&T syntax) assembly.
|
|
//
|
|
// Bug: gas in `intel_syntax noprefix' mode interprets the symbol `Sp' in an
|
|
// instruction as a reference to the register named sp, and if you try to
|
|
// reference a symbol `Sp' (e.g. `mov ECX, OFFSET Sp') then it gets lowercased
|
|
// before being looked up in the symbol table. This creates spurious
|
|
// `undefined symbol' errors when linking. Workaround: Do not use `noprefix'
|
|
// mode, and decorate all register names with percent signs.
|
|
O << "\t.intel_syntax\n";
|
|
Mang = new Mangler(M, EmitCygwin);
|
|
return false; // success
|
|
}
|
|
|
|
// SwitchSection - Switch to the specified section of the executable if we are
|
|
// not already in it!
|
|
//
|
|
static void SwitchSection(std::ostream &OS, std::string &CurSection,
|
|
const char *NewSection) {
|
|
if (CurSection != NewSection) {
|
|
CurSection = NewSection;
|
|
if (!CurSection.empty())
|
|
OS << "\t" << NewSection << "\n";
|
|
}
|
|
}
|
|
|
|
bool Printer::doFinalization(Module &M) {
|
|
const TargetData &TD = TM.getTargetData();
|
|
std::string CurSection;
|
|
|
|
// Print out module-level global variables here.
|
|
for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I)
|
|
if (I->hasInitializer()) { // External global require no code
|
|
O << "\n\n";
|
|
std::string name = Mang->getValueName(I);
|
|
Constant *C = I->getInitializer();
|
|
unsigned Size = TD.getTypeSize(C->getType());
|
|
unsigned Align = TD.getTypeAlignment(C->getType());
|
|
|
|
if (C->isNullValue() &&
|
|
(I->hasLinkOnceLinkage() || I->hasInternalLinkage() ||
|
|
I->hasWeakLinkage() /* FIXME: Verify correct */)) {
|
|
SwitchSection(O, CurSection, ".data");
|
|
if (I->hasInternalLinkage())
|
|
O << "\t.local " << name << "\n";
|
|
|
|
O << "\t.comm " << name << "," << TD.getTypeSize(C->getType())
|
|
<< "," << (unsigned)TD.getTypeAlignment(C->getType());
|
|
O << "\t\t# ";
|
|
WriteAsOperand(O, I, true, true, &M);
|
|
O << "\n";
|
|
} else {
|
|
switch (I->getLinkage()) {
|
|
case GlobalValue::LinkOnceLinkage:
|
|
case GlobalValue::WeakLinkage: // FIXME: Verify correct for weak.
|
|
// Nonnull linkonce -> weak
|
|
O << "\t.weak " << name << "\n";
|
|
SwitchSection(O, CurSection, "");
|
|
O << "\t.section\t.llvm.linkonce.d." << name << ",\"aw\",@progbits\n";
|
|
break;
|
|
|
|
case GlobalValue::AppendingLinkage:
|
|
// FIXME: appending linkage variables should go into a section of
|
|
// their name or something. For now, just emit them as external.
|
|
case GlobalValue::ExternalLinkage:
|
|
// If external or appending, declare as a global symbol
|
|
O << "\t.globl " << name << "\n";
|
|
// FALL THROUGH
|
|
case GlobalValue::InternalLinkage:
|
|
if (C->isNullValue())
|
|
SwitchSection(O, CurSection, ".bss");
|
|
else
|
|
SwitchSection(O, CurSection, ".data");
|
|
break;
|
|
}
|
|
|
|
O << "\t.align " << Align << "\n";
|
|
O << "\t.type " << name << ",@object\n";
|
|
O << "\t.size " << name << "," << Size << "\n";
|
|
O << name << ":\t\t\t\t# ";
|
|
WriteAsOperand(O, I, true, true, &M);
|
|
O << " = ";
|
|
WriteAsOperand(O, C, false, false, &M);
|
|
O << "\n";
|
|
emitGlobalConstant(C);
|
|
}
|
|
}
|
|
|
|
delete Mang;
|
|
return false; // success
|
|
}
|