Tim Renouf 2a99fa2c08 [AMDGPU] added writelane intrinsic ... Summary: For use by LLPC SPV_AMD_shader_ballot extension. The v_writelane instruction was already implemented for use by SGPR spilling, but I had to add an extra dummy operand tied to the destination, to represent that all lanes except the selected one keep the old value of the destination register. .ll test changes were due to schedule changes caused by that new operand. Differential Revision: https://reviews.llvm.org/D42838 llvm-svn: 326353		2018-02-28 19:10:32 +00:00
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llvm	[AMDGPU] added writelane intrinsic	2018-02-28 19:10:32 +00:00
llvm-c	Allow 0 to be a valid value pruning interval in C LTO API. Value 0 will cause garbage collector to run. This matches the behavior in C++ LTO API.	2018-02-15 23:29:21 +00:00