maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/lib/Target/RISCV
History
Sam Elliott 856d5c5817 [RISCV] Allow ABI Names in Inline Assembly Constraints 
Summary:
Clang will replace references to registers using ABI names in inline
assembly constraints with references to architecture names, but other
frontends do not. LLVM uses the regular assembly parser to parse inline asm,
so inline assembly strings can contain references to registers using their
ABI names.

This patch adds support for parsing constraints using either the ABI name or
the architectural register name. This means we do not need to implement the
ABI name replacement code in every single frontend, especially those like
Rust which are a very thin shim on top of LLVM IR's inline asm, and that
constraints can more closely match the assembly strings they refer to.

Reviewers: asb, simoncook

Reviewed By: simoncook

Subscribers: hiraditya, rbar, johnrusso, JDevlieghere, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65947

llvm-svn: 368303
 		2019-08-08 14:59:16 +00:00
..
AsmParser [RISCV] Add Custom Parser for Atomic Memory Operands 2019-08-01 12:42:31 +00:00
Disassembler Revert CMake: Make most target symbols hidden by default 2019-06-11 03:21:13 +00:00
MCTargetDesc [RISCV] Add Custom Parser for Atomic Memory Operands 2019-08-01 12:42:31 +00:00
TargetInfo Revert CMake: Make most target symbols hidden by default 2019-06-11 03:21:13 +00:00
Utils [RISCV] Avoid signed integer overflow UB in RISCVMatInt::generateInstSeq 2019-07-18 04:02:58 +00:00
CMakeLists.txt [RISCV] Add RISCV-specific TargetTransformInfo 2019-06-21 13:36:09 +00:00
LLVMBuild.txt [RISCV] Add RISCV-specific TargetTransformInfo 2019-06-21 13:36:09 +00:00
RISCV.h Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
RISCV.td [RISCV][NFC] Replace hard-coded CSR duplication with symbolic references 2019-07-05 12:16:40 +00:00
RISCVAsmPrinter.cpp [RISCV] Support z and i operand modifiers 2019-07-08 05:00:26 +00:00
RISCVCallingConv.td [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
RISCVExpandPseudoInsts.cpp [RISCV] Add lowering of global TLS addresses 2019-06-19 08:40:59 +00:00
RISCVFrameLowering.cpp [RISCV] Minimal stack realignment support 2019-08-08 14:40:54 +00:00
RISCVFrameLowering.h Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
RISCVISelDAGToDAG.cpp [RISCV] Support @llvm.readcyclecounter() Intrinsic 2019-07-05 12:35:21 +00:00
RISCVISelLowering.cpp [RISCV] Allow ABI Names in Inline Assembly Constraints 2019-08-08 14:59:16 +00:00
RISCVISelLowering.h [RISCV] Support 'f' Inline Assembly Constraint 2019-07-31 09:45:55 +00:00
RISCVInstrFormats.td [RISCV] Implement pseudo instructions for load/store from a symbol address. 2019-02-20 03:31:32 +00:00
RISCVInstrFormatsC.td Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
RISCVInstrInfo.cpp [RISCV] Don't acccess an invalidated iterator in RISCVInstrInfo::removeBranch 2019-07-18 03:23:47 +00:00
RISCVInstrInfo.h Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI 2019-01-25 20:22:49 +00:00
RISCVInstrInfo.td [RISCV] Match GNU tools canonical JALR and add aliases 2019-07-16 04:56:43 +00:00
RISCVInstrInfoA.td [RISCV] Add Custom Parser for Atomic Memory Operands 2019-08-01 12:42:31 +00:00
RISCVInstrInfoC.td [RISCV] Add implied zero offset load/store alias patterns 2019-02-21 14:09:34 +00:00
RISCVInstrInfoD.td [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
RISCVInstrInfoF.td [RISCV][NFC] Replace hard-coded CSR duplication with symbolic references 2019-07-05 12:16:40 +00:00
RISCVInstrInfoM.td [RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M 2019-01-25 05:11:34 +00:00
RISCVMCInstLower.cpp [RISCV] Add lowering of global TLS addresses 2019-06-19 08:40:59 +00:00
RISCVMachineFunctionInfo.h [RISCV] Delete a ctor that is commented out. NFC 2019-07-05 08:25:14 +00:00
RISCVMergeBaseOffset.cpp Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
RISCVRegisterInfo.cpp CodeGen: Introduce a class for registers 2019-06-24 15:50:29 +00:00
RISCVRegisterInfo.h CodeGen: Introduce a class for registers 2019-06-24 15:50:29 +00:00
RISCVRegisterInfo.td [RISCV] Allow fp as an alias of s0 2019-03-11 21:35:26 +00:00
RISCVSubtarget.cpp [RISCV] Add basic RV32E definitions and MC layer support 2019-03-22 11:21:40 +00:00
RISCVSubtarget.h [RISCV] Add basic RV32E definitions and MC layer support 2019-03-22 11:21:40 +00:00
RISCVSystemOperands.td [RISCV][NFC] Replace hard-coded CSR duplication with symbolic references 2019-07-05 12:16:40 +00:00
RISCVTargetMachine.cpp [RISCV] Add RISCV-specific TargetTransformInfo 2019-06-21 13:36:09 +00:00
RISCVTargetMachine.h [RISCV] Add RISCV-specific TargetTransformInfo 2019-06-21 13:36:09 +00:00
RISCVTargetObjectFile.cpp [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
RISCVTargetObjectFile.h [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
RISCVTargetTransformInfo.cpp [RISCV] Fix RISCVTTIImpl::getIntImmCost for immediates where getMinSignedBits() > 64 2019-07-09 10:56:18 +00:00
RISCVTargetTransformInfo.h [RISCV] Add RISCV-specific TargetTransformInfo 2019-06-21 13:36:09 +00:00