llvm-project/llvm/test/CodeGen
Oliver Stannard 6ae3d310bd Revert "Reland [AArch64][MachineOutliner] Return address signing for outlined functions"
This reverts commit cec2d5c174.

Reverting because this is still creating outlined functions with return
address signing instructions with mismatches SP values. For example:

  int *volatile v;

  void foo(int x) {
    int a[x];
    v = &a[0];
    v = &a[0];
    v = &a[0];
    v = &a[0];
    v = &a[0];
    v = &a[0];
  }

  void bar(int x) {
    int a[x];
    v = 0;
    v = &a[0];
    v = &a[0];
    v = &a[0];
    v = &a[0];
    v = &a[0];
  }

This generates these two outlined functions, both of which modify SP
between the paciasp and retaa instructions:

  $ clang --target=aarch64-arm-none-eabi -march=armv8.3-a -c test2.c -o - -S -Oz -mbranch-protection=pac-ret+leaf
  ...
  OUTLINED_FUNCTION_0:                    // @OUTLINED_FUNCTION_0
          .cfi_sections .debug_frame
          .cfi_startproc
  // %bb.0:
          paciasp
          .cfi_negate_ra_state
          mov     w8, w0
          lsl     x8, x8, #2
          add     x8, x8, #15             // =15
          mov     x9, sp
          and     x8, x8, #0x7fffffff0
          sub     x8, x9, x8
          mov     x29, sp
          mov     sp, x8
          adrp    x9, v
          retaa
  ...
  OUTLINED_FUNCTION_1:                    // @OUTLINED_FUNCTION_1
          .cfi_startproc
  // %bb.0:
          paciasp
          .cfi_negate_ra_state
          str     x8, [x9, :lo12:v]
          str     x8, [x9, :lo12:v]
          str     x8, [x9, :lo12:v]
          str     x8, [x9, :lo12:v]
          str     x8, [x9, :lo12:v]
          mov     sp, x29
          retaa
2019-12-11 12:06:20 +00:00
..
AArch64 Revert "Reland [AArch64][MachineOutliner] Return address signing for outlined functions" 2019-12-11 12:06:20 +00:00
AMDGPU [MBP] Avoid tail duplication if it can't bring benefit 2019-12-06 09:53:53 -08:00
ARC
ARM [LegalizeTypes] Bugfixes for big-endian targets when handling BITCASTs 2019-12-10 11:22:35 +01:00
AVR
BPF [BPF] put not-section-attribute externs into BTF ".extern" data section 2019-12-10 11:45:17 -08:00
Generic [CodeGen] [ExpandReduction] Fix the bug for ExpandReduction() when vector size isn't power of 2 2019-11-02 23:59:12 -04:00
Hexagon [ModuloSchedule] Fix a bug in experimental expander 2019-11-23 16:01:47 -08:00
Inputs
Lanai
MIR [llvm][MIRVRegNamerUtil] Adding hashing against MachineInstr flags. 2019-12-10 20:16:14 -05:00
MSP430 [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (4) 2019-11-13 09:23:08 +01:00
Mips Handle BUNDLE instructions in MipsAsmPrinter 2019-12-04 11:30:00 +00:00
NVPTX [NVPTX] Added llvm.nvvm.mma.m8n8k4.* intrinsics 2019-10-28 13:55:30 -07:00
PowerPC [PowerPC][NFC] add test case for lwa - loop ds form prep 2019-12-11 06:10:11 -05:00
RISCV [RISCV] Fix mir-target-flags.ll 2019-12-09 13:51:08 +00:00
SPARC Temporarily run machine-verifier once in test/CodeGen/SPARC/fp128.ll, so that 2019-12-03 11:21:52 +01:00
SystemZ [FPEnv] Constrained FCmp intrinsics 2019-12-07 11:28:39 +01:00
Thumb Revert "ARM-Darwin: keep the frame register reserved even if not updated." 2019-12-06 10:59:26 -08:00
Thumb2 [ARM][LowOverheadLoops] Remove dead loop update instructions. 2019-12-11 10:20:19 +00:00
WebAssembly [WebAssembly] Fix miscompile of select with and 2019-11-15 16:22:01 -08:00
WinCFGuard [WinCFG] Handle constant casts carefully in .gfids emission 2019-11-01 13:32:03 -07:00
WinEH
X86 [X86] Split v64i1 arguments into 2 v32i1s that will be promoted to v32i8 under min-legal-vector-width=256 2019-12-10 17:29:02 -08:00
XCore