Jon Roelofs 5fb979dd06 [llvm][test] Add missing FileCheck colons. NFC		2020-05-21 09:29:27 -06:00
..
AArch64	[llvm][test] Add missing FileCheck colons. NFC	2020-05-21 09:29:27 -06:00
AMDGPU	[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC	2020-05-21 09:29:27 -06:00
ARC	…
ARM	[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC	2020-05-21 09:29:27 -06:00
AVR	[AVR] Fix I/O instructions on XMEGA	2020-05-17 19:46:09 +12:00
BPF	[BPF] Return fail if disassembled insn registers out of range	2020-05-18 18:53:23 -07:00
Generic	[MachineDebugify] Insert synthetic DBG_VALUE instructions	2020-04-22 17:03:39 -07:00
Hexagon	[ModuloSchedule] Fix epilogue peeling with illegal phi.	2020-05-07 10:04:05 -07:00
Inputs	…
Lanai	…
MIR	[AMDGPU] Avoid hard-coded line numbers in error message checks	2020-04-23 21:06:09 +01:00
MSP430	…
Mips	[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC	2020-05-21 09:29:27 -06:00
NVPTX	[llvm] Fix missing FileCheck directive colons	2020-04-06 09:59:08 -06:00
PowerPC	[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC	2020-05-21 09:29:27 -06:00
RISCV	[RISCV] Support Constant Pools in Load/Store Peephole	2020-05-11 19:20:38 +01:00
SPARC	…
SystemZ	[SystemZ] Eliminate the need to create a zero vector by reusing the VPERM mask.	2020-05-19 09:37:19 +02:00
Thumb	[ARM] Don't shrink STM if it would cause an unknown base register store	2020-04-22 14:50:42 +01:00
Thumb2	[HardwareLoops] llvm.loop.decrement.reg definition	2020-05-21 10:48:16 +01:00
VE	[VE] Update branch instructions	2020-04-28 09:41:01 +02:00
WebAssembly	[WebAssembly] Fix bug in custom shuffle combine	2020-05-19 12:54:15 -07:00
WinCFGuard	…
WinEH	…
X86	[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC	2020-05-21 09:29:27 -06:00
XCore	…