forked from OSchip/llvm-project
8f8cdd00da
Summary: The relocation is missing mask so an address that has non-zero bits in 47:43 may overwrite the register number. (Frequently shows up as target register changed to `xzr`....) Reviewers: t.p.northover, lhames Subscribers: davide, aemerson, rengolin, llvm-commits Differential Revision: https://reviews.llvm.org/D27609 llvm-svn: 289880 |
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| .. | ||
| Interpreter | ||
| MCJIT | ||
| OrcLazy | ||
| OrcMCJIT | ||
| RuntimeDyld | ||
| 2010-01-15-UndefValue.ll | ||
| fma3-jit.ll | ||
| frem.ll | ||
| lit.local.cfg | ||
| mov64zext32.ll | ||
| test-interp-vec-arithm_float.ll | ||
| test-interp-vec-arithm_int.ll | ||
| test-interp-vec-cast.ll | ||
| test-interp-vec-insertelement.ll | ||
| test-interp-vec-insertextractvalue.ll | ||
| test-interp-vec-loadstore.ll | ||
| test-interp-vec-logical.ll | ||
| test-interp-vec-select.ll | ||
| test-interp-vec-setcond-fp.ll | ||
| test-interp-vec-setcond-int.ll | ||
| test-interp-vec-shift.ll | ||
| test-interp-vec-shuffle.ll | ||