forked from OSchip/llvm-project
373 lines
16 KiB
LLVM
373 lines
16 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
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define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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; CHECK-LABEL: vuzpi8:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vuzp.8 d17, d16
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; CHECK-NEXT: vadd.i8 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%tmp5 = add <8 x i8> %tmp3, %tmp4
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ret <8 x i8> %tmp5
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}
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define <16 x i8> @vuzpi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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; CHECK-LABEL: vuzpi8_Qres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
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; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0]
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; CHECK-NEXT: vuzp.8 [[LDR0]], [[LDR1]]
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; CHECK-NEXT: vmov r0, r1, [[LDR0]]
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; CHECK-NEXT: vmov r2, r3, [[LDR1]]
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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ret <16 x i8> %tmp3
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}
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define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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; CHECK-LABEL: vuzpi16:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vuzp.16 d17, d16
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; CHECK-NEXT: vadd.i16 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%tmp5 = add <4 x i16> %tmp3, %tmp4
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ret <4 x i16> %tmp5
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}
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define <8 x i16> @vuzpi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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; CHECK-LABEL: vuzpi16_Qres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
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; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0]
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; CHECK-NEXT: vuzp.16 [[LDR0]], [[LDR1]]
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; CHECK-NEXT: vmov r0, r1, [[LDR0]]
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; CHECK-NEXT: vmov r2, r3, [[LDR1]]
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
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ret <8 x i16> %tmp3
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}
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; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.
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define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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; CHECK-LABEL: vuzpQi8:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vuzp.8 q9, q8
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; CHECK-NEXT: vadd.i8 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
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%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
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%tmp5 = add <16 x i8> %tmp3, %tmp4
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ret <16 x i8> %tmp5
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}
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define <32 x i8> @vuzpQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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; CHECK-LABEL: vuzpQi8_QQres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
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; CHECK-NEXT: vuzp.8 q9, q8
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; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
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; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
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ret <32 x i8> %tmp3
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}
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define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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; CHECK-LABEL: vuzpQi16:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vuzp.16 q9, q8
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; CHECK-NEXT: vadd.i16 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = load <8 x i16>, <8 x i16>* %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%tmp5 = add <8 x i16> %tmp3, %tmp4
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ret <8 x i16> %tmp5
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}
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define <16 x i16> @vuzpQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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; CHECK-LABEL: vuzpQi16_QQres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
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; CHECK-NEXT: vuzp.16 q9, q8
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; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
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; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = load <8 x i16>, <8 x i16>* %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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ret <16 x i16> %tmp3
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}
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define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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; CHECK-LABEL: vuzpQi32:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vuzp.32 q9, q8
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; CHECK-NEXT: vadd.i32 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = load <4 x i32>, <4 x i32>* %B
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%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%tmp5 = add <4 x i32> %tmp3, %tmp4
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ret <4 x i32> %tmp5
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}
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define <8 x i32> @vuzpQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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; CHECK-LABEL: vuzpQi32_QQres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
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; CHECK-NEXT: vuzp.32 q9, q8
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; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
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; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = load <4 x i32>, <4 x i32>* %B
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%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
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ret <8 x i32> %tmp3
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}
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define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
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; CHECK-LABEL: vuzpQf:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vuzp.32 q9, q8
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; CHECK-NEXT: vadd.f32 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x float>, <4 x float>* %A
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%tmp2 = load <4 x float>, <4 x float>* %B
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%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%tmp5 = fadd <4 x float> %tmp3, %tmp4
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ret <4 x float> %tmp5
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}
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define <8 x float> @vuzpQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind {
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; CHECK-LABEL: vuzpQf_QQres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
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; CHECK-NEXT: vuzp.32 q9, q8
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; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
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; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x float>, <4 x float>* %A
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%tmp2 = load <4 x float>, <4 x float>* %B
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%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
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ret <8 x float> %tmp3
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}
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; Undef shuffle indices should not prevent matching to VUZP:
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define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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; CHECK-LABEL: vuzpi8_undef:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vuzp.8 d17, d16
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; CHECK-NEXT: vadd.i8 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 8, i32 10, i32 12, i32 14>
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%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15>
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%tmp5 = add <8 x i8> %tmp3, %tmp4
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ret <8 x i8> %tmp5
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}
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define <16 x i8> @vuzpi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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; CHECK-LABEL: vuzpi8_undef_Qres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
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; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0]
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; CHECK-NEXT: vuzp.8 [[LDR0]], [[LDR1]]
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; CHECK-NEXT: vmov r0, r1, [[LDR0]]
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; CHECK-NEXT: vmov r2, r3, [[LDR1]]
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15>
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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; CHECK-LABEL: vuzpQi16_undef:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vuzp.16 q9, q8
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; CHECK-NEXT: vadd.i16 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = load <8 x i16>, <8 x i16>* %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14>
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%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15>
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%tmp5 = add <8 x i16> %tmp3, %tmp4
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ret <8 x i16> %tmp5
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}
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define <16 x i16> @vuzpQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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; CHECK-LABEL: vuzpQi16_undef_QQres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
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; CHECK-NEXT: vuzp.16 q9, q8
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; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
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; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = load <8 x i16>, <8 x i16>* %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15>
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ret <16 x i16> %tmp3
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}
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define <8 x i16> @vuzp_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) {
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entry:
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; CHECK-LABEL: vuzp_lower_shufflemask_undef
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; CHECK: vuzp
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 3, i32 5, i32 7>
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ret <8 x i16> %0
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}
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define <4 x i32> @vuzp_lower_shufflemask_zeroed(<2 x i32>* %A, <2 x i32>* %B) {
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entry:
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; CHECK-LABEL: vuzp_lower_shufflemask_zeroed
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; CHECK-NOT: vtrn
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; CHECK: vuzp
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = load <2 x i32>, <2 x i32>* %B
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%0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 0, i32 0, i32 1, i32 3>
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ret <4 x i32> %0
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}
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define void @vuzp_rev_shufflemask_vtrn(<2 x i32>* %A, <2 x i32>* %B, <4 x i32>* %C) {
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entry:
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; CHECK-LABEL: vuzp_rev_shufflemask_vtrn
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; CHECK-NOT: vtrn
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; CHECK: vuzp
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = load <2 x i32>, <2 x i32>* %B
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%0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 1, i32 3, i32 0, i32 2>
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store <4 x i32> %0, <4 x i32>* %C
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ret void
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}
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|
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define <8 x i8> @vuzp_trunc(<8 x i8> %in0, <8 x i8> %in1, <8 x i32> %cmp0, <8 x i32> %cmp1) {
|
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; In order to create the select we need to truncate the vcgt result from a vector of i32 to a vector of i8.
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; This results in a build_vector with mismatched types. We will generate two vmovn.i32 instructions to
|
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; truncate from i32 to i16 and one vuzp to perform the final truncation for i8.
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; CHECK-LABEL: vuzp_trunc
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; CHECK: vmovn.i32
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; CHECK: vmovn.i32
|
|
; CHECK: vuzp
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|
; CHECK: vbsl
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|
%c = icmp ult <8 x i32> %cmp0, %cmp1
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%res = select <8 x i1> %c, <8 x i8> %in0, <8 x i8> %in1
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|
ret <8 x i8> %res
|
|
}
|
|
|
|
; Shuffle the result from the compare with a <4 x i8>.
|
|
; We need to extend the loaded <4 x i8> to <4 x i16>. Otherwise we wouldn't be able
|
|
; to perform the vuzp and get the vbsl mask.
|
|
define <8 x i8> @vuzp_trunc_and_shuffle(<8 x i8> %tr0, <8 x i8> %tr1,
|
|
<4 x i32> %cmp0, <4 x i32> %cmp1, <4 x i8> *%cmp2_ptr) {
|
|
; CHECK-LABEL: vuzp_trunc_and_shuffle
|
|
; CHECK: vmovl
|
|
; CHECK: vuzp
|
|
; CHECK: vbsl
|
|
%cmp2_load = load <4 x i8>, <4 x i8> * %cmp2_ptr, align 4
|
|
%cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1>
|
|
%c0 = icmp ult <4 x i32> %cmp0, %cmp1
|
|
%c = shufflevector <4 x i1> %c0, <4 x i1> %cmp2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
|
%rv = select <8 x i1> %c, <8 x i8> %tr0, <8 x i8> %tr1
|
|
ret <8 x i8> %rv
|
|
}
|
|
|
|
; Use an undef value for the <4 x i8> that is being shuffled with the compare result.
|
|
; This produces a build_vector with some of the operands undefs.
|
|
define <8 x i8> @vuzp_trunc_and_shuffle_undef_right(<8 x i8> %tr0, <8 x i8> %tr1,
|
|
<4 x i32> %cmp0, <4 x i32> %cmp1, <4 x i8> *%cmp2_ptr) {
|
|
; CHECK-LABEL: vuzp_trunc_and_shuffle_undef_right
|
|
; CHECK: vuzp
|
|
; CHECK: vbsl
|
|
%cmp2_load = load <4 x i8>, <4 x i8> * %cmp2_ptr, align 4
|
|
%cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1>
|
|
%c0 = icmp ult <4 x i32> %cmp0, %cmp1
|
|
%c = shufflevector <4 x i1> %c0, <4 x i1> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
|
%rv = select <8 x i1> %c, <8 x i8> %tr0, <8 x i8> %tr1
|
|
ret <8 x i8> %rv
|
|
}
|
|
|
|
define <8 x i8> @vuzp_trunc_and_shuffle_undef_left(<8 x i8> %tr0, <8 x i8> %tr1,
|
|
<4 x i32> %cmp0, <4 x i32> %cmp1, <4 x i8> *%cmp2_ptr) {
|
|
; CHECK-LABEL: vuzp_trunc_and_shuffle_undef_left
|
|
; CHECK: vuzp
|
|
; CHECK: vbsl
|
|
%cmp2_load = load <4 x i8>, <4 x i8> * %cmp2_ptr, align 4
|
|
%cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1>
|
|
%c0 = icmp ult <4 x i32> %cmp0, %cmp1
|
|
%c = shufflevector <4 x i1> undef, <4 x i1> %c0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
|
%rv = select <8 x i1> %c, <8 x i8> %tr0, <8 x i8> %tr1
|
|
ret <8 x i8> %rv
|
|
}
|
|
|
|
; We're using large data types here, and we have to fill with undef values until we
|
|
; get some vector size that we can represent.
|
|
define <10 x i8> @vuzp_wide_type(<10 x i8> %tr0, <10 x i8> %tr1,
|
|
<5 x i32> %cmp0, <5 x i32> %cmp1, <5 x i8> *%cmp2_ptr) {
|
|
; CHECK-LABEL: vuzp_wide_type
|
|
; CHECK: vbsl
|
|
%cmp2_load = load <5 x i8>, <5 x i8> * %cmp2_ptr, align 4
|
|
%cmp2 = trunc <5 x i8> %cmp2_load to <5 x i1>
|
|
%c0 = icmp ult <5 x i32> %cmp0, %cmp1
|
|
%c = shufflevector <5 x i1> %c0, <5 x i1> %cmp2, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
|
|
%rv = select <10 x i1> %c, <10 x i8> %tr0, <10 x i8> %tr1
|
|
ret <10 x i8> %rv
|
|
}
|