Jim Grosbach d359571120 ARM refactoring assembly parsing of memory address operands. ... Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845		2011-08-03 23:50:40 +00:00
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ARM	ARM refactoring assembly parsing of memory address operands.	2011-08-03 23:50:40 +00:00
MBlaze	Teach the MBlaze disassembler to disassemble special purpose registers.	2010-12-20 21:18:04 +00:00
X86	Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.	2011-07-16 02:41:28 +00:00