forked from OSchip/llvm-project
258 lines
9.6 KiB
C++
258 lines
9.6 KiB
C++
//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
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//
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// This file implements the LiveVariable analysis pass.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/CFG.h"
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#include "Support/DepthFirstIterator.h"
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static RegisterAnalysis<LiveVariables> X("livevars", "Live Variable Analysis");
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void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
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const BasicBlock *BB) {
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const std::pair<MachineBasicBlock*,unsigned> &Info = BBMap.find(BB)->second;
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MachineBasicBlock *MBB = Info.first;
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unsigned BBNum = Info.second;
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// Check to see if this basic block is one of the killing blocks. If so,
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// remove it...
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for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
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if (VRInfo.Kills[i].first == MBB) {
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VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
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break;
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}
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if (MBB == VRInfo.DefBlock) return; // Terminate recursion
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if (VRInfo.AliveBlocks.size() <= BBNum)
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VRInfo.AliveBlocks.resize(BBNum+1); // Make space...
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if (VRInfo.AliveBlocks[BBNum])
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return; // We already know the block is live
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// Mark the variable known alive in this bb
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VRInfo.AliveBlocks[BBNum] = true;
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for (pred_const_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI)
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MarkVirtRegAliveInBlock(VRInfo, *PI);
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}
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void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
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MachineInstr *MI) {
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// Check to see if this basic block is already a kill block...
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if (!VRInfo.Kills.empty() && VRInfo.Kills.back().first == MBB) {
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// Yes, this register is killed in this basic block already. Increase the
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// live range by updating the kill instruction.
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VRInfo.Kills.back().second = MI;
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return;
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}
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#ifndef NDEBUG
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for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
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assert(VRInfo.Kills[i].first != MBB && "entry should be at end!");
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#endif
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assert(MBB != VRInfo.DefBlock && "Should have kill for defblock!");
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// Add a new kill entry for this basic block.
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VRInfo.Kills.push_back(std::make_pair(MBB, MI));
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// Update all dominating blocks to mark them known live.
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const BasicBlock *BB = MBB->getBasicBlock();
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for (pred_const_iterator PI = pred_begin(BB), E = pred_end(BB);
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PI != E; ++PI)
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MarkVirtRegAliveInBlock(VRInfo, *PI);
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}
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void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
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if (PhysRegInfo[Reg]) {
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PhysRegInfo[Reg] = MI;
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PhysRegUsed[Reg] = true;
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} else if (const unsigned *AliasSet = RegInfo->getAliasSet(Reg)) {
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for (; unsigned NReg = AliasSet[0]; ++AliasSet)
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if (MachineInstr *LastUse = PhysRegInfo[NReg]) {
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PhysRegInfo[NReg] = MI;
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PhysRegUsed[NReg] = true;
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}
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}
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}
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void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
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// Does this kill a previous version of this register?
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if (MachineInstr *LastUse = PhysRegInfo[Reg]) {
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if (PhysRegUsed[Reg])
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RegistersKilled.insert(std::make_pair(LastUse, Reg));
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else
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RegistersDead.insert(std::make_pair(LastUse, Reg));
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} else if (const unsigned *AliasSet = RegInfo->getAliasSet(Reg)) {
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for (; unsigned NReg = AliasSet[0]; ++AliasSet)
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if (MachineInstr *LastUse = PhysRegInfo[NReg]) {
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if (PhysRegUsed[NReg])
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RegistersKilled.insert(std::make_pair(LastUse, NReg));
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else
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RegistersDead.insert(std::make_pair(LastUse, NReg));
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PhysRegInfo[NReg] = 0; // Kill the aliased register
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}
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}
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PhysRegInfo[Reg] = MI;
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PhysRegUsed[Reg] = false;
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}
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bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
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// Build BBMap...
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unsigned BBNum = 0;
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
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BBMap[I->getBasicBlock()] = std::make_pair(I, BBNum++);
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// PhysRegInfo - Keep track of which instruction was the last use of a
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// physical register. This is a purely local property, because all physical
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// register references as presumed dead across basic blocks.
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//
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MachineInstr *PhysRegInfoA[MRegisterInfo::FirstVirtualRegister];
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bool PhysRegUsedA[MRegisterInfo::FirstVirtualRegister];
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std::fill(PhysRegInfoA, PhysRegInfoA+MRegisterInfo::FirstVirtualRegister,
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(MachineInstr*)0);
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PhysRegInfo = PhysRegInfoA;
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PhysRegUsed = PhysRegUsedA;
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const TargetInstrInfo &TII = MF.getTarget().getInstrInfo();
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RegInfo = MF.getTarget().getRegisterInfo();
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/// Get some space for a respectable number of registers...
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VirtRegInfo.resize(64);
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// Calculate live variable information in depth first order on the CFG of the
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// function. This guarantees that we will see the definition of a virtual
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// register before its uses due to dominance properties of SSA (except for PHI
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// nodes, which are treated as a special case).
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//
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const BasicBlock *Entry = MF.getFunction()->begin();
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for (df_iterator<const BasicBlock*> DFI = df_begin(Entry), E = df_end(Entry);
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DFI != E; ++DFI) {
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const BasicBlock *BB = *DFI;
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std::pair<MachineBasicBlock*, unsigned> &BBRec = BBMap.find(BB)->second;
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MachineBasicBlock *MBB = BBRec.first;
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unsigned BBNum = BBRec.second;
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// Loop over all of the instructions, processing them.
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I) {
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MachineInstr *MI = *I;
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const TargetInstrDescriptor &MID = TII.get(MI->getOpcode());
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// Process all of the operands of the instruction...
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unsigned NumOperandsToProcess = MI->getNumOperands();
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// Unless it is a PHI node. In this case, ONLY process the DEF, not any
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// of the uses. They will be handled in other basic blocks.
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if (MI->getOpcode() == TargetInstrInfo::PHI)
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NumOperandsToProcess = 1;
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// Loop over implicit uses, using them.
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if (const unsigned *ImplicitUses = MID.ImplicitUses)
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for (unsigned i = 0; ImplicitUses[i]; ++i)
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HandlePhysRegUse(ImplicitUses[i], MI);
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// Process all explicit uses...
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for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.opIsUse() || MO.opIsDefAndUse()) {
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if (MO.isVirtualRegister() && !MO.getVRegValueOrNull()) {
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unsigned RegIdx = MO.getReg()-MRegisterInfo::FirstVirtualRegister;
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HandleVirtRegUse(getVarInfo(RegIdx), MBB, MI);
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} else if (MO.isPhysicalRegister() && MO.getReg() != 0
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/// FIXME: This is a gross hack, due to us not being able to
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/// say that some registers are defined on entry to the
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/// function. 5 = ESP
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&& MO.getReg() != 5
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) {
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HandlePhysRegUse(MO.getReg(), MI);
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}
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}
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}
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// Loop over implicit defs, defining them.
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if (const unsigned *ImplicitDefs = MID.ImplicitDefs)
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for (unsigned i = 0; ImplicitDefs[i]; ++i)
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HandlePhysRegDef(ImplicitDefs[i], MI);
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// Process all explicit defs...
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for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.opIsDef() || MO.opIsDefAndUse()) {
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if (MO.isVirtualRegister()) {
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unsigned RegIdx = MO.getReg()-MRegisterInfo::FirstVirtualRegister;
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VarInfo &VRInfo = getVarInfo(RegIdx);
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assert(VRInfo.DefBlock == 0 && "Variable multiply defined!");
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VRInfo.DefBlock = MBB; // Created here...
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VRInfo.DefInst = MI;
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VRInfo.Kills.push_back(std::make_pair(MBB, MI)); // Defaults to dead
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} else if (MO.isPhysicalRegister() && MO.getReg() != 0
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/// FIXME: This is a gross hack, due to us not being able to
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/// say that some registers are defined on entry to the
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/// function. 5 = ESP
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&& MO.getReg() != 5
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) {
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HandlePhysRegDef(MO.getReg(), MI);
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}
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}
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}
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}
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// Handle any virtual assignments from PHI nodes which might be at the
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// bottom of this basic block. We check all of our successor blocks to see
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// if they have PHI nodes, and if so, we simulate an assignment at the end
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// of the current block.
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for (succ_const_iterator I = succ_begin(BB), E = succ_end(BB); I != E; ++I){
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MachineBasicBlock *Succ = BBMap.find(*I)->second.first;
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// PHI nodes are guaranteed to be at the top of the block...
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for (MachineBasicBlock::iterator I = Succ->begin(), E = Succ->end();
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I != E && (*I)->getOpcode() == TargetInstrInfo::PHI; ++I) {
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for (unsigned i = 1; ; i += 2)
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if ((*I)->getOperand(i+1).getMachineBasicBlock() == MBB) {
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MachineOperand &MO = (*I)->getOperand(i);
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if (!MO.getVRegValueOrNull()) {
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unsigned RegIdx = MO.getReg()-MRegisterInfo::FirstVirtualRegister;
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VarInfo &VRInfo = getVarInfo(RegIdx);
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// Only mark it alive only in the block we are representing...
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MarkVirtRegAliveInBlock(VRInfo, BB);
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break; // Found the PHI entry for this block...
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}
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}
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}
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}
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// Loop over PhysRegInfo, killing any registers that are available at the
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// end of the basic block. This also resets the PhysRegInfo map.
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for (unsigned i = 0, e = MRegisterInfo::FirstVirtualRegister; i != e; ++i)
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if (PhysRegInfo[i])
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HandlePhysRegDef(i, 0);
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}
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BBMap.clear();
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// Convert the information we have gathered into VirtRegInfo and transform it
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// into a form usable by RegistersKilled.
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//
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for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i)
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for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) {
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if (VirtRegInfo[i].Kills[j].second == VirtRegInfo[i].DefInst)
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RegistersDead.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
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i + MRegisterInfo::FirstVirtualRegister));
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else
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RegistersKilled.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
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i + MRegisterInfo::FirstVirtualRegister));
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}
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return false;
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}
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