forked from OSchip/llvm-project
125 lines
3.0 KiB
YAML
125 lines
3.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE2
|
|
|
|
--- |
|
|
define void @test_sub_v16i8() {
|
|
%ret = sub <16 x i8> undef, undef
|
|
ret void
|
|
}
|
|
|
|
define void @test_sub_v8i16() {
|
|
%ret = sub <8 x i16> undef, undef
|
|
ret void
|
|
}
|
|
|
|
define void @test_sub_v4i32() {
|
|
%ret = sub <4 x i32> undef, undef
|
|
ret void
|
|
}
|
|
|
|
define void @test_sub_v2i64() {
|
|
%ret = sub <2 x i64> undef, undef
|
|
ret void
|
|
}
|
|
...
|
|
---
|
|
name: test_sub_v16i8
|
|
alignment: 4
|
|
legalized: false
|
|
regBankSelected: false
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
body: |
|
|
bb.1 (%ir-block.0):
|
|
liveins: $xmm0, $xmm1
|
|
|
|
; ALL-LABEL: name: test_sub_v16i8
|
|
; ALL: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
|
|
; ALL: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
|
|
; ALL: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[DEF]], [[DEF1]]
|
|
; ALL: RET 0
|
|
%0(<16 x s8>) = IMPLICIT_DEF
|
|
%1(<16 x s8>) = IMPLICIT_DEF
|
|
%2(<16 x s8>) = G_SUB %0, %1
|
|
$xmm0 = COPY %2
|
|
RET 0
|
|
|
|
...
|
|
---
|
|
name: test_sub_v8i16
|
|
alignment: 4
|
|
legalized: false
|
|
regBankSelected: false
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
body: |
|
|
bb.1 (%ir-block.0):
|
|
liveins: $xmm0, $xmm1
|
|
|
|
; ALL-LABEL: name: test_sub_v8i16
|
|
; ALL: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
|
|
; ALL: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
|
|
; ALL: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[DEF]], [[DEF1]]
|
|
; ALL: RET 0
|
|
%0(<8 x s16>) = IMPLICIT_DEF
|
|
%1(<8 x s16>) = IMPLICIT_DEF
|
|
%2(<8 x s16>) = G_SUB %0, %1
|
|
$xmm0 = COPY %2
|
|
RET 0
|
|
|
|
...
|
|
---
|
|
name: test_sub_v4i32
|
|
alignment: 4
|
|
legalized: false
|
|
regBankSelected: false
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
body: |
|
|
bb.1 (%ir-block.0):
|
|
liveins: $xmm0, $xmm1
|
|
|
|
; ALL-LABEL: name: test_sub_v4i32
|
|
; ALL: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
|
|
; ALL: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
|
|
; ALL: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[DEF]], [[DEF1]]
|
|
; ALL: RET 0
|
|
%0(<4 x s32>) = IMPLICIT_DEF
|
|
%1(<4 x s32>) = IMPLICIT_DEF
|
|
%2(<4 x s32>) = G_SUB %0, %1
|
|
$xmm0 = COPY %2
|
|
RET 0
|
|
|
|
...
|
|
---
|
|
name: test_sub_v2i64
|
|
alignment: 4
|
|
legalized: false
|
|
regBankSelected: false
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
body: |
|
|
bb.1 (%ir-block.0):
|
|
liveins: $xmm0, $xmm1
|
|
|
|
; ALL-LABEL: name: test_sub_v2i64
|
|
; ALL: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
|
|
; ALL: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
|
|
; ALL: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[DEF]], [[DEF1]]
|
|
; ALL: RET 0
|
|
%0(<2 x s64>) = IMPLICIT_DEF
|
|
%1(<2 x s64>) = IMPLICIT_DEF
|
|
%2(<2 x s64>) = G_SUB %0, %1
|
|
$xmm0 = COPY %2
|
|
RET 0
|
|
|
|
...
|