forked from OSchip/llvm-project
615 lines
16 KiB
YAML
615 lines
16 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
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# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
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--- |
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define i8 @test_zext_i1toi8(i1 %a) {
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%r = zext i1 %a to i8
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ret i8 %r
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}
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define i16 @test_zext_i1toi16(i1 %a) {
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%r = zext i1 %a to i16
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ret i16 %r
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}
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define i32 @test_zext_i1(i8 %a) {
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%val = trunc i8 %a to i1
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%r = zext i1 %val to i32
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ret i32 %r
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}
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define i16 @test_zext_i8toi16(i8 %val) {
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%r = zext i8 %val to i16
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ret i16 %r
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}
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define i32 @test_zext_i8(i8 %val) {
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%r = zext i8 %val to i32
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ret i32 %r
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}
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define i32 @test_zext_i16(i16 %val) {
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%r = zext i16 %val to i32
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ret i32 %r
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}
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define i8 @test_sext_i1toi8(i1 %a) {
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%r = sext i1 %a to i8
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ret i8 %r
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}
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define i16 @test_sext_i1toi16(i1 %a) {
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%r = sext i1 %a to i16
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ret i16 %r
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}
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define i32 @test_sext_i1(i8 %a) {
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%val = trunc i8 %a to i1
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%r = sext i1 %val to i32
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ret i32 %r
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}
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define i16 @test_sext_i8toi16(i8 %val) {
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%r = sext i8 %val to i16
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ret i16 %r
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}
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define i32 @test_sext_i8(i8 %val) {
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%r = sext i8 %val to i32
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ret i32 %r
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}
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define i32 @test_sext_i16(i16 %val) {
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%r = sext i16 %val to i32
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ret i32 %r
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}
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define void @test_anyext_i1toi8(i1 %a) {
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ret void
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}
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define void @test_anyext_i1toi16(i1 %a) {
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ret void
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}
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define void @test_anyext_i1(i8 %a) {
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ret void
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}
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define void @test_anyext_i8toi16(i8 %val) {
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ret void
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}
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define void @test_anyext_i8(i8 %val) {
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ret void
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}
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define void @test_anyext_i16(i16 %val) {
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ret void
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}
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...
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---
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name: test_zext_i1toi8
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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- { id: 2, class: _, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; X32-LABEL: name: test_zext_i1toi8
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; X32: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
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; X32: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
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; X32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
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; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
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; X32: $al = COPY [[AND]](s8)
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; X32: RET 0, implicit $al
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; X64-LABEL: name: test_zext_i1toi8
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; X64: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
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; X64: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
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; X64: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
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; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
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; X64: $al = COPY [[AND]](s8)
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; X64: RET 0, implicit $al
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%1:_(s32) = COPY $edi
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%0:_(s1) = G_TRUNC %1(s32)
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%2:_(s8) = G_ZEXT %0(s1)
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$al = COPY %2(s8)
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RET 0, implicit $al
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...
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---
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name: test_zext_i1toi16
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; X32-LABEL: name: test_zext_i1toi16
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; X32: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
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; X32: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
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; X32: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; X32: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
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; X32: $ax = COPY [[AND]](s16)
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; X32: RET 0, implicit $ax
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; X64-LABEL: name: test_zext_i1toi16
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; X64: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
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; X64: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
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; X64: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; X64: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
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; X64: $ax = COPY [[AND]](s16)
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; X64: RET 0, implicit $ax
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%1:_(s32) = COPY $edi
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%0:_(s1) = G_TRUNC %1(s32)
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%2:_(s16) = G_ZEXT %0(s1)
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$ax = COPY %2(s16)
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RET 0, implicit $ax
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...
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---
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name: test_zext_i1
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; X32-LABEL: name: test_zext_i1
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; X32: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
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; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
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; X32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
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; X32: $eax = COPY [[AND]](s32)
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; X32: RET 0, implicit $eax
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; X64-LABEL: name: test_zext_i1
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; X64: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
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; X64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
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; X64: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
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; X64: $eax = COPY [[AND]](s32)
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; X64: RET 0, implicit $eax
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%0(s8) = COPY $dil
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%1(s1) = G_TRUNC %0(s8)
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%2(s32) = G_ZEXT %1(s1)
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$eax = COPY %2(s32)
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RET 0, implicit $eax
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...
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---
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name: test_zext_i8toi16
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; X32-LABEL: name: test_zext_i8toi16
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; X32: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
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; X32: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[COPY]](s8)
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; X32: $ax = COPY [[ZEXT]](s16)
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; X32: RET 0, implicit $ax
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; X64-LABEL: name: test_zext_i8toi16
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; X64: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
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; X64: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[COPY]](s8)
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; X64: $ax = COPY [[ZEXT]](s16)
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; X64: RET 0, implicit $ax
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%0(s8) = COPY $dil
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%1(s16) = G_ZEXT %0(s8)
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$ax = COPY %1(s16)
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RET 0, implicit $ax
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...
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---
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name: test_zext_i8
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; X32-LABEL: name: test_zext_i8
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; X32: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
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; X32: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s8)
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; X32: $eax = COPY [[ZEXT]](s32)
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; X32: RET 0, implicit $eax
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; X64-LABEL: name: test_zext_i8
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; X64: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
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; X64: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s8)
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; X64: $eax = COPY [[ZEXT]](s32)
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; X64: RET 0, implicit $eax
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%0(s8) = COPY $dil
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%1(s32) = G_ZEXT %0(s8)
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$eax = COPY %1(s32)
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RET 0, implicit $eax
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...
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---
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name: test_zext_i16
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; X32-LABEL: name: test_zext_i16
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; X32: [[COPY:%[0-9]+]]:_(s16) = COPY $di
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; X32: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s16)
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; X32: $eax = COPY [[ZEXT]](s32)
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; X32: RET 0, implicit $eax
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; X64-LABEL: name: test_zext_i16
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; X64: [[COPY:%[0-9]+]]:_(s16) = COPY $di
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; X64: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s16)
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; X64: $eax = COPY [[ZEXT]](s32)
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; X64: RET 0, implicit $eax
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%0(s16) = COPY $di
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%1(s32) = G_ZEXT %0(s16)
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$eax = COPY %1(s32)
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RET 0, implicit $eax
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...
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---
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name: test_sext_i1toi8
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; X32-LABEL: name: test_sext_i1toi8
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; X32: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
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; X32: $al = COPY [[DEF]](s8)
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; X32: RET 0, implicit $al
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; X64-LABEL: name: test_sext_i1toi8
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; X64: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
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; X64: $al = COPY [[DEF]](s8)
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; X64: RET 0, implicit $al
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%0(s1) = G_IMPLICIT_DEF
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%1(s8) = G_SEXT %0(s1)
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$al = COPY %1(s8)
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RET 0, implicit $al
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...
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---
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name: test_sext_i1toi16
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; X32-LABEL: name: test_sext_i1toi16
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; X32: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
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; X32: $ax = COPY [[DEF]](s16)
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; X32: RET 0, implicit $ax
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; X64-LABEL: name: test_sext_i1toi16
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; X64: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
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; X64: $ax = COPY [[DEF]](s16)
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; X64: RET 0, implicit $ax
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%0(s1) = G_IMPLICIT_DEF
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%1(s16) = G_SEXT %0(s1)
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$ax = COPY %1(s16)
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RET 0, implicit $ax
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...
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---
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name: test_sext_i1
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; X32-LABEL: name: test_sext_i1
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; X32: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
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; X32: $eax = COPY [[DEF]](s32)
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; X32: RET 0, implicit $eax
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; X64-LABEL: name: test_sext_i1
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; X64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
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; X64: $eax = COPY [[DEF]](s32)
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; X64: RET 0, implicit $eax
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%0(s1) = G_IMPLICIT_DEF
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%2(s32) = G_SEXT %0(s1)
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$eax = COPY %2(s32)
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RET 0, implicit $eax
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...
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---
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name: test_sext_i8toi16
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; X32-LABEL: name: test_sext_i8toi16
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; X32: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
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; X32: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[COPY]](s8)
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; X32: $ax = COPY [[SEXT]](s16)
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; X32: RET 0, implicit $ax
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; X64-LABEL: name: test_sext_i8toi16
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; X64: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
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; X64: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[COPY]](s8)
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; X64: $ax = COPY [[SEXT]](s16)
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; X64: RET 0, implicit $ax
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%0(s8) = COPY $dil
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%1(s16) = G_SEXT %0(s8)
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$ax = COPY %1(s16)
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RET 0, implicit $ax
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...
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---
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name: test_sext_i8
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; X32-LABEL: name: test_sext_i8
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; X32: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
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; X32: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s8)
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; X32: $eax = COPY [[SEXT]](s32)
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; X32: RET 0, implicit $eax
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; X64-LABEL: name: test_sext_i8
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; X64: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
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; X64: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s8)
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; X64: $eax = COPY [[SEXT]](s32)
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; X64: RET 0, implicit $eax
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%0(s8) = COPY $dil
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%1(s32) = G_SEXT %0(s8)
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$eax = COPY %1(s32)
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RET 0, implicit $eax
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...
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---
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name: test_sext_i16
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; X32-LABEL: name: test_sext_i16
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; X32: [[COPY:%[0-9]+]]:_(s16) = COPY $di
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; X32: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s16)
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; X32: $eax = COPY [[SEXT]](s32)
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; X32: RET 0, implicit $eax
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; X64-LABEL: name: test_sext_i16
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; X64: [[COPY:%[0-9]+]]:_(s16) = COPY $di
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; X64: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s16)
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; X64: $eax = COPY [[SEXT]](s32)
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; X64: RET 0, implicit $eax
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%0(s16) = COPY $di
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%1(s32) = G_SEXT %0(s16)
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$eax = COPY %1(s32)
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RET 0, implicit $eax
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|
...
|
|
---
|
|
name: test_anyext_i1toi8
|
|
alignment: 4
|
|
legalized: false
|
|
regBankSelected: false
|
|
registers:
|
|
- { id: 0, class: _, preferred-register: '' }
|
|
- { id: 1, class: _, preferred-register: '' }
|
|
- { id: 2, class: _, preferred-register: '' }
|
|
body: |
|
|
bb.1 (%ir-block.0):
|
|
liveins: $edi
|
|
|
|
; X32-LABEL: name: test_anyext_i1toi8
|
|
; X32: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
|
|
; X32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
|
|
; X32: $al = COPY [[TRUNC]](s8)
|
|
; X32: RET 0, implicit $al
|
|
; X64-LABEL: name: test_anyext_i1toi8
|
|
; X64: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
|
|
; X64: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
|
|
; X64: $al = COPY [[TRUNC]](s8)
|
|
; X64: RET 0, implicit $al
|
|
%0(s32) = COPY $edi
|
|
%1(s1) = G_TRUNC %0(s32)
|
|
%2(s8) = G_ANYEXT %1(s1)
|
|
$al = COPY %2(s8)
|
|
RET 0, implicit $al
|
|
|
|
...
|
|
---
|
|
name: test_anyext_i1toi16
|
|
alignment: 4
|
|
legalized: false
|
|
regBankSelected: false
|
|
registers:
|
|
- { id: 0, class: _, preferred-register: '' }
|
|
- { id: 1, class: _, preferred-register: '' }
|
|
- { id: 2, class: _, preferred-register: '' }
|
|
body: |
|
|
bb.1 (%ir-block.0):
|
|
liveins: $edi
|
|
|
|
; X32-LABEL: name: test_anyext_i1toi16
|
|
; X32: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
|
|
; X32: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
|
|
; X32: $ax = COPY [[TRUNC]](s16)
|
|
; X32: RET 0, implicit $ax
|
|
; X64-LABEL: name: test_anyext_i1toi16
|
|
; X64: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
|
|
; X64: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
|
|
; X64: $ax = COPY [[TRUNC]](s16)
|
|
; X64: RET 0, implicit $ax
|
|
%0(s32) = COPY $edi
|
|
%1(s1) = G_TRUNC %0(s32)
|
|
%2(s16) = G_ANYEXT %1(s1)
|
|
$ax = COPY %2(s16)
|
|
RET 0, implicit $ax
|
|
|
|
...
|
|
---
|
|
name: test_anyext_i1
|
|
alignment: 4
|
|
legalized: false
|
|
regBankSelected: false
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
body: |
|
|
bb.1 (%ir-block.0):
|
|
liveins: $edi
|
|
|
|
; X32-LABEL: name: test_anyext_i1
|
|
; X32: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
|
|
; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
|
|
; X32: $eax = COPY [[ANYEXT]](s32)
|
|
; X32: RET 0, implicit $eax
|
|
; X64-LABEL: name: test_anyext_i1
|
|
; X64: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
|
|
; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
|
|
; X64: $eax = COPY [[ANYEXT]](s32)
|
|
; X64: RET 0, implicit $eax
|
|
%0(s8) = COPY $dil
|
|
%1(s1) = G_TRUNC %0(s8)
|
|
%2(s32) = G_ANYEXT %1(s1)
|
|
$eax = COPY %2(s32)
|
|
RET 0, implicit $eax
|
|
|
|
...
|
|
---
|
|
name: test_anyext_i8toi16
|
|
alignment: 4
|
|
legalized: false
|
|
regBankSelected: false
|
|
registers:
|
|
- { id: 0, class: _, preferred-register: '' }
|
|
- { id: 1, class: _, preferred-register: '' }
|
|
body: |
|
|
bb.1 (%ir-block.0):
|
|
liveins: $edi
|
|
|
|
; X32-LABEL: name: test_anyext_i8toi16
|
|
; X32: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
|
|
; X32: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
|
|
; X32: $ax = COPY [[ANYEXT]](s16)
|
|
; X32: RET 0, implicit $ax
|
|
; X64-LABEL: name: test_anyext_i8toi16
|
|
; X64: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
|
|
; X64: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
|
|
; X64: $ax = COPY [[ANYEXT]](s16)
|
|
; X64: RET 0, implicit $ax
|
|
%0(s8) = COPY $dil
|
|
%1(s16) = G_ANYEXT %0(s8)
|
|
$ax = COPY %1(s16)
|
|
RET 0, implicit $ax
|
|
|
|
...
|
|
---
|
|
name: test_anyext_i8
|
|
alignment: 4
|
|
legalized: false
|
|
regBankSelected: false
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
body: |
|
|
bb.1 (%ir-block.0):
|
|
liveins: $edi
|
|
|
|
; X32-LABEL: name: test_anyext_i8
|
|
; X32: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
|
|
; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
|
|
; X32: $eax = COPY [[ANYEXT]](s32)
|
|
; X32: RET 0, implicit $eax
|
|
; X64-LABEL: name: test_anyext_i8
|
|
; X64: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
|
|
; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
|
|
; X64: $eax = COPY [[ANYEXT]](s32)
|
|
; X64: RET 0, implicit $eax
|
|
%0(s8) = COPY $dil
|
|
%1(s32) = G_ANYEXT %0(s8)
|
|
$eax = COPY %1(s32)
|
|
RET 0, implicit $eax
|
|
|
|
...
|
|
---
|
|
name: test_anyext_i16
|
|
alignment: 4
|
|
legalized: false
|
|
regBankSelected: false
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
body: |
|
|
bb.1 (%ir-block.0):
|
|
liveins: $edi
|
|
|
|
; X32-LABEL: name: test_anyext_i16
|
|
; X32: [[COPY:%[0-9]+]]:_(s16) = COPY $di
|
|
; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s16)
|
|
; X32: $eax = COPY [[ANYEXT]](s32)
|
|
; X32: RET 0, implicit $eax
|
|
; X64-LABEL: name: test_anyext_i16
|
|
; X64: [[COPY:%[0-9]+]]:_(s16) = COPY $di
|
|
; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s16)
|
|
; X64: $eax = COPY [[ANYEXT]](s32)
|
|
; X64: RET 0, implicit $eax
|
|
%0(s16) = COPY $di
|
|
%1(s32) = G_ANYEXT %0(s16)
|
|
$eax = COPY %1(s32)
|
|
RET 0, implicit $eax
|
|
|
|
...
|