forked from OSchip/llvm-project
220 lines
8.3 KiB
C++
220 lines
8.3 KiB
C++
//===- RegAllocEvictionAdvisor.h - Interference resolution ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_REGALLOCEVICTIONADVISOR_H
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#define LLVM_CODEGEN_REGALLOCEVICTIONADVISOR_H
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#include "AllocationOrder.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/LiveRegMatrix.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Register.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/Config/llvm-config.h"
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#include "llvm/Pass.h"
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namespace llvm {
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using SmallVirtRegSet = SmallSet<Register, 16>;
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// Live ranges pass through a number of stages as we try to allocate them.
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// Some of the stages may also create new live ranges:
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//
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// - Region splitting.
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// - Per-block splitting.
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// - Local splitting.
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// - Spilling.
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//
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// Ranges produced by one of the stages skip the previous stages when they are
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// dequeued. This improves performance because we can skip interference checks
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// that are unlikely to give any results. It also guarantees that the live
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// range splitting algorithm terminates, something that is otherwise hard to
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// ensure.
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enum LiveRangeStage {
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/// Newly created live range that has never been queued.
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RS_New,
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/// Only attempt assignment and eviction. Then requeue as RS_Split.
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RS_Assign,
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/// Attempt live range splitting if assignment is impossible.
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RS_Split,
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/// Attempt more aggressive live range splitting that is guaranteed to make
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/// progress. This is used for split products that may not be making
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/// progress.
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RS_Split2,
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/// Live range will be spilled. No more splitting will be attempted.
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RS_Spill,
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/// Live range is in memory. Because of other evictions, it might get moved
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/// in a register in the end.
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RS_Memory,
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/// There is nothing more we can do to this live range. Abort compilation
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/// if it can't be assigned.
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RS_Done
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};
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/// Cost of evicting interference - used by default advisor, and the eviction
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/// chain heuristic in RegAllocGreedy.
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// FIXME: this can be probably made an implementation detail of the default
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// advisor, if the eviction chain logic can be refactored.
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struct EvictionCost {
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unsigned BrokenHints = 0; ///< Total number of broken hints.
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float MaxWeight = 0; ///< Maximum spill weight evicted.
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EvictionCost() = default;
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bool isMax() const { return BrokenHints == ~0u; }
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void setMax() { BrokenHints = ~0u; }
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void setBrokenHints(unsigned NHints) { BrokenHints = NHints; }
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bool operator<(const EvictionCost &O) const {
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return std::tie(BrokenHints, MaxWeight) <
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std::tie(O.BrokenHints, O.MaxWeight);
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}
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};
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/// Interface to the eviction advisor, which is responsible for making a
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/// decision as to which live ranges should be evicted (if any).
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class RAGreedy;
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class RegAllocEvictionAdvisor {
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public:
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RegAllocEvictionAdvisor(const RegAllocEvictionAdvisor &) = delete;
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RegAllocEvictionAdvisor(RegAllocEvictionAdvisor &&) = delete;
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virtual ~RegAllocEvictionAdvisor() = default;
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/// Find a physical register that can be freed by evicting the FixedRegisters,
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/// or return NoRegister. The eviction decision is assumed to be correct (i.e.
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/// no fixed live ranges are evicted) and profitable.
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virtual MCRegister tryFindEvictionCandidate(
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const LiveInterval &VirtReg, const AllocationOrder &Order,
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uint8_t CostPerUseLimit, const SmallVirtRegSet &FixedRegisters) const = 0;
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/// Find out if we can evict the live ranges occupying the given PhysReg,
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/// which is a hint (preferred register) for VirtReg.
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virtual bool
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canEvictHintInterference(const LiveInterval &VirtReg, MCRegister PhysReg,
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const SmallVirtRegSet &FixedRegisters) const = 0;
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/// Returns true if the given \p PhysReg is a callee saved register and has
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/// not been used for allocation yet.
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bool isUnusedCalleeSavedReg(MCRegister PhysReg) const;
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protected:
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RegAllocEvictionAdvisor(const MachineFunction &MF, const RAGreedy &RA);
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Register canReassign(const LiveInterval &VirtReg, Register PrevReg) const;
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// Get the upper limit of elements in the given Order we need to analize.
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// TODO: is this heuristic, we could consider learning it.
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Optional<unsigned> getOrderLimit(const LiveInterval &VirtReg,
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const AllocationOrder &Order,
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unsigned CostPerUseLimit) const;
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// Determine if it's worth trying to allocate this reg, given the
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// CostPerUseLimit
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// TODO: this is a heuristic component we could consider learning, too.
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bool canAllocatePhysReg(unsigned CostPerUseLimit, MCRegister PhysReg) const;
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const MachineFunction &MF;
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const RAGreedy &RA;
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LiveRegMatrix *const Matrix;
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LiveIntervals *const LIS;
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VirtRegMap *const VRM;
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MachineRegisterInfo *const MRI;
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const TargetRegisterInfo *const TRI;
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const RegisterClassInfo &RegClassInfo;
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const ArrayRef<uint8_t> RegCosts;
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/// Run or not the local reassignment heuristic. This information is
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/// obtained from the TargetSubtargetInfo.
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const bool EnableLocalReassign;
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private:
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unsigned NextCascade = 1;
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};
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/// ImmutableAnalysis abstraction for fetching the Eviction Advisor. We model it
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/// as an analysis to decouple the user from the implementation insofar as
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/// dependencies on other analyses goes. The motivation for it being an
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/// immutable pass is twofold:
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/// - in the ML implementation case, the evaluator is stateless but (especially
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/// in the development mode) expensive to set up. With an immutable pass, we set
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/// it up once.
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/// - in the 'development' mode ML case, we want to capture the training log
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/// during allocation (this is a log of features encountered and decisions
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/// made), and then measure a score, potentially a few steps after allocation
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/// completes. So we need the properties of an immutable pass to keep the logger
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/// state around until we can make that measurement.
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///
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/// Because we need to offer additional services in 'development' mode, the
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/// implementations of this analysis need to implement RTTI support.
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class RegAllocEvictionAdvisorAnalysis : public ImmutablePass {
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public:
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enum class AdvisorMode : int { Default, Release, Development };
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RegAllocEvictionAdvisorAnalysis(AdvisorMode Mode)
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: ImmutablePass(ID), Mode(Mode){};
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static char ID;
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/// Get an advisor for the given context (i.e. machine function, etc)
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virtual std::unique_ptr<RegAllocEvictionAdvisor>
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getAdvisor(const MachineFunction &MF, const RAGreedy &RA) = 0;
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AdvisorMode getAdvisorMode() const { return Mode; }
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protected:
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// This analysis preserves everything, and subclasses may have additional
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// requirements.
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesAll();
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}
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private:
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StringRef getPassName() const override;
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const AdvisorMode Mode;
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};
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/// Specialization for the API used by the analysis infrastructure to create
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/// an instance of the eviction advisor.
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template <> Pass *callDefaultCtor<RegAllocEvictionAdvisorAnalysis>();
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RegAllocEvictionAdvisorAnalysis *createReleaseModeAdvisor();
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RegAllocEvictionAdvisorAnalysis *createDevelopmentModeAdvisor();
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// TODO: move to RegAllocEvictionAdvisor.cpp when we move implementation
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// out of RegAllocGreedy.cpp
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class DefaultEvictionAdvisor : public RegAllocEvictionAdvisor {
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public:
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DefaultEvictionAdvisor(const MachineFunction &MF, const RAGreedy &RA)
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: RegAllocEvictionAdvisor(MF, RA) {}
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private:
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MCRegister tryFindEvictionCandidate(const LiveInterval &,
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const AllocationOrder &, uint8_t,
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const SmallVirtRegSet &) const override;
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bool canEvictHintInterference(const LiveInterval &, MCRegister,
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const SmallVirtRegSet &) const override;
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bool canEvictInterferenceBasedOnCost(const LiveInterval &, MCRegister, bool,
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EvictionCost &,
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const SmallVirtRegSet &) const;
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bool shouldEvict(const LiveInterval &A, bool, const LiveInterval &B,
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bool) const;
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};
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} // namespace llvm
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#endif // LLVM_CODEGEN_REGALLOCEVICTIONADVISOR_H
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