forked from OSchip/llvm-project
308 lines
12 KiB
C++
308 lines
12 KiB
C++
//===- RegAllocEvictionAdvisor.cpp - eviction advisor ---------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Implementation of the default eviction advisor and of the Analysis pass.
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//
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//===----------------------------------------------------------------------===//
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#include "RegAllocEvictionAdvisor.h"
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#include "RegAllocGreedy.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/RegisterClassInfo.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Pass.h"
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#include "llvm/PassRegistry.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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static cl::opt<RegAllocEvictionAdvisorAnalysis::AdvisorMode> Mode(
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"regalloc-enable-advisor", cl::Hidden, cl::ZeroOrMore,
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cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default),
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cl::desc("Enable regalloc advisor mode"),
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cl::values(
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clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default,
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"default", "Default"),
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clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release,
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"release", "precompiled"),
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clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development,
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"development", "for training")));
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static cl::opt<bool> EnableLocalReassignment(
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"enable-local-reassign", cl::Hidden,
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cl::desc("Local reassignment can yield better allocation decisions, but "
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"may be compile time intensive"),
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cl::init(false));
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cl::opt<unsigned> EvictInterferenceCutoff(
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"regalloc-eviction-max-interference-cutoff", cl::Hidden,
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cl::desc("Number of interferences after which we declare "
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"an interference unevictable and bail out. This "
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"is a compilation cost-saving consideration. To "
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"disable, pass a very large number."),
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cl::init(10));
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#define DEBUG_TYPE "regalloc"
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#ifdef LLVM_HAVE_TF_AOT_REGALLOCEVICTMODEL
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#define LLVM_HAVE_TF_AOT
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#endif
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char RegAllocEvictionAdvisorAnalysis::ID = 0;
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INITIALIZE_PASS(RegAllocEvictionAdvisorAnalysis, "regalloc-evict",
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"Regalloc eviction policy", false, true)
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namespace {
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class DefaultEvictionAdvisorAnalysis final
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: public RegAllocEvictionAdvisorAnalysis {
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public:
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DefaultEvictionAdvisorAnalysis(bool NotAsRequested)
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: RegAllocEvictionAdvisorAnalysis(AdvisorMode::Default),
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NotAsRequested(NotAsRequested) {}
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// support for isa<> and dyn_cast.
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static bool classof(const RegAllocEvictionAdvisorAnalysis *R) {
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return R->getAdvisorMode() == AdvisorMode::Default;
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}
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private:
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std::unique_ptr<RegAllocEvictionAdvisor>
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getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override {
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return std::make_unique<DefaultEvictionAdvisor>(MF, RA);
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}
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bool doInitialization(Module &M) override {
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if (NotAsRequested)
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M.getContext().emitError("Requested regalloc eviction advisor analysis "
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"could be created. Using default");
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return RegAllocEvictionAdvisorAnalysis::doInitialization(M);
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}
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const bool NotAsRequested;
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};
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} // namespace
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template <> Pass *llvm::callDefaultCtor<RegAllocEvictionAdvisorAnalysis>() {
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Pass *Ret = nullptr;
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switch (Mode) {
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case RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default:
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Ret = new DefaultEvictionAdvisorAnalysis(/*NotAsRequested*/ false);
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break;
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case RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development:
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#if defined(LLVM_HAVE_TF_API)
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Ret = createDevelopmentModeAdvisor();
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#endif
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break;
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case RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release:
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#if defined(LLVM_HAVE_TF_AOT)
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Ret = createReleaseModeAdvisor();
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#endif
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break;
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}
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if (Ret)
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return Ret;
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return new DefaultEvictionAdvisorAnalysis(/*NotAsRequested*/ true);
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}
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StringRef RegAllocEvictionAdvisorAnalysis::getPassName() const {
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switch (getAdvisorMode()) {
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case AdvisorMode::Default:
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return "Default Regalloc Eviction Advisor";
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case AdvisorMode::Release:
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return "Release mode Regalloc Eviction Advisor";
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case AdvisorMode::Development:
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return "Development mode Regalloc Eviction Advisor";
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}
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llvm_unreachable("Unknown advisor kind");
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}
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RegAllocEvictionAdvisor::RegAllocEvictionAdvisor(const MachineFunction &MF,
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const RAGreedy &RA)
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: MF(MF), RA(RA), Matrix(RA.getInterferenceMatrix()),
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LIS(RA.getLiveIntervals()), VRM(RA.getVirtRegMap()),
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MRI(&VRM->getRegInfo()), TRI(MF.getSubtarget().getRegisterInfo()),
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RegClassInfo(RA.getRegClassInfo()), RegCosts(TRI->getRegisterCosts(MF)),
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EnableLocalReassign(EnableLocalReassignment ||
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MF.getSubtarget().enableRALocalReassignment(
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MF.getTarget().getOptLevel())) {}
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/// shouldEvict - determine if A should evict the assigned live range B. The
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/// eviction policy defined by this function together with the allocation order
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/// defined by enqueue() decides which registers ultimately end up being split
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/// and spilled.
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///
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/// Cascade numbers are used to prevent infinite loops if this function is a
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/// cyclic relation.
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///
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/// @param A The live range to be assigned.
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/// @param IsHint True when A is about to be assigned to its preferred
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/// register.
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/// @param B The live range to be evicted.
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/// @param BreaksHint True when B is already assigned to its preferred register.
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bool DefaultEvictionAdvisor::shouldEvict(const LiveInterval &A, bool IsHint,
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const LiveInterval &B,
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bool BreaksHint) const {
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bool CanSplit = RA.getExtraInfo().getStage(B) < RS_Spill;
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// Be fairly aggressive about following hints as long as the evictee can be
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// split.
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if (CanSplit && IsHint && !BreaksHint)
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return true;
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if (A.weight() > B.weight()) {
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LLVM_DEBUG(dbgs() << "should evict: " << B << " w= " << B.weight() << '\n');
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return true;
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}
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return false;
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}
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/// canEvictHintInterference - return true if the interference for VirtReg
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/// on the PhysReg, which is VirtReg's hint, can be evicted in favor of VirtReg.
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bool DefaultEvictionAdvisor::canEvictHintInterference(
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const LiveInterval &VirtReg, MCRegister PhysReg,
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const SmallVirtRegSet &FixedRegisters) const {
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EvictionCost MaxCost;
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MaxCost.setBrokenHints(1);
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return canEvictInterferenceBasedOnCost(VirtReg, PhysReg, true, MaxCost,
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FixedRegisters);
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}
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/// canEvictInterferenceBasedOnCost - Return true if all interferences between
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/// VirtReg and PhysReg can be evicted.
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///
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/// @param VirtReg Live range that is about to be assigned.
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/// @param PhysReg Desired register for assignment.
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/// @param IsHint True when PhysReg is VirtReg's preferred register.
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/// @param MaxCost Only look for cheaper candidates and update with new cost
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/// when returning true.
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/// @returns True when interference can be evicted cheaper than MaxCost.
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bool DefaultEvictionAdvisor::canEvictInterferenceBasedOnCost(
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const LiveInterval &VirtReg, MCRegister PhysReg, bool IsHint,
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EvictionCost &MaxCost, const SmallVirtRegSet &FixedRegisters) const {
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// It is only possible to evict virtual register interference.
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if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg)
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return false;
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bool IsLocal = VirtReg.empty() || LIS->intervalIsInOneMBB(VirtReg);
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// Find VirtReg's cascade number. This will be unassigned if VirtReg was never
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// involved in an eviction before. If a cascade number was assigned, deny
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// evicting anything with the same or a newer cascade number. This prevents
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// infinite eviction loops.
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//
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// This works out so a register without a cascade number is allowed to evict
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// anything, and it can be evicted by anything.
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unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg());
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EvictionCost Cost;
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for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
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LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
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// If there is 10 or more interferences, chances are one is heavier.
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const auto &Interferences = Q.interferingVRegs(EvictInterferenceCutoff);
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if (Interferences.size() >= EvictInterferenceCutoff)
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return false;
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// Check if any interfering live range is heavier than MaxWeight.
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for (const LiveInterval *Intf : reverse(Interferences)) {
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assert(Register::isVirtualRegister(Intf->reg()) &&
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"Only expecting virtual register interference from query");
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// Do not allow eviction of a virtual register if we are in the middle
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// of last-chance recoloring and this virtual register is one that we
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// have scavenged a physical register for.
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if (FixedRegisters.count(Intf->reg()))
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return false;
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// Never evict spill products. They cannot split or spill.
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if (RA.getExtraInfo().getStage(*Intf) == RS_Done)
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return false;
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// Once a live range becomes small enough, it is urgent that we find a
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// register for it. This is indicated by an infinite spill weight. These
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// urgent live ranges get to evict almost anything.
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//
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// Also allow urgent evictions of unspillable ranges from a strictly
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// larger allocation order.
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bool Urgent =
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!VirtReg.isSpillable() &&
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(Intf->isSpillable() ||
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RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg())) <
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RegClassInfo.getNumAllocatableRegs(
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MRI->getRegClass(Intf->reg())));
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// Only evict older cascades or live ranges without a cascade.
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unsigned IntfCascade = RA.getExtraInfo().getCascade(Intf->reg());
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if (Cascade <= IntfCascade) {
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if (!Urgent)
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return false;
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// We permit breaking cascades for urgent evictions. It should be the
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// last resort, though, so make it really expensive.
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Cost.BrokenHints += 10;
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}
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// Would this break a satisfied hint?
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bool BreaksHint = VRM->hasPreferredPhys(Intf->reg());
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// Update eviction cost.
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Cost.BrokenHints += BreaksHint;
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Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight());
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// Abort if this would be too expensive.
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if (!(Cost < MaxCost))
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return false;
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if (Urgent)
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continue;
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// Apply the eviction policy for non-urgent evictions.
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if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
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return false;
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// If !MaxCost.isMax(), then we're just looking for a cheap register.
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// Evicting another local live range in this case could lead to suboptimal
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// coloring.
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if (!MaxCost.isMax() && IsLocal && LIS->intervalIsInOneMBB(*Intf) &&
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(!EnableLocalReassign || !canReassign(*Intf, PhysReg))) {
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return false;
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}
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}
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}
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MaxCost = Cost;
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return true;
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}
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MCRegister DefaultEvictionAdvisor::tryFindEvictionCandidate(
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const LiveInterval &VirtReg, const AllocationOrder &Order,
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uint8_t CostPerUseLimit, const SmallVirtRegSet &FixedRegisters) const {
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// Keep track of the cheapest interference seen so far.
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EvictionCost BestCost;
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BestCost.setMax();
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MCRegister BestPhys;
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auto MaybeOrderLimit = getOrderLimit(VirtReg, Order, CostPerUseLimit);
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if (!MaybeOrderLimit)
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return MCRegister::NoRegister;
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unsigned OrderLimit = *MaybeOrderLimit;
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// When we are just looking for a reduced cost per use, don't break any
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// hints, and only evict smaller spill weights.
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if (CostPerUseLimit < uint8_t(~0u)) {
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BestCost.BrokenHints = 0;
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BestCost.MaxWeight = VirtReg.weight();
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}
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for (auto I = Order.begin(), E = Order.getOrderLimitEnd(OrderLimit); I != E;
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++I) {
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MCRegister PhysReg = *I;
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assert(PhysReg);
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if (!canAllocatePhysReg(CostPerUseLimit, PhysReg) ||
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!canEvictInterferenceBasedOnCost(VirtReg, PhysReg, false, BestCost,
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FixedRegisters))
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continue;
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// Best so far.
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BestPhys = PhysReg;
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// Stop if the hint can be used.
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if (I.isHint())
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break;
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}
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return BestPhys;
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}
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