forked from OSchip/llvm-project
762 lines
30 KiB
C++
762 lines
30 KiB
C++
//===- PhiElimination.cpp - Eliminate PHI nodes by inserting copies -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass eliminates machine instruction PHI nodes by inserting copy
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// instructions. This destroys SSA information, but is the desired input for
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// some register allocators.
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//
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//===----------------------------------------------------------------------===//
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#include "PHIEliminationUtils.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <iterator>
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#include <utility>
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using namespace llvm;
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#define DEBUG_TYPE "phi-node-elimination"
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static cl::opt<bool>
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DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false),
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cl::Hidden, cl::desc("Disable critical edge splitting "
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"during PHI elimination"));
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static cl::opt<bool>
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SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false),
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cl::Hidden, cl::desc("Split all critical edges during "
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"PHI elimination"));
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static cl::opt<bool> NoPhiElimLiveOutEarlyExit(
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"no-phi-elim-live-out-early-exit", cl::init(false), cl::Hidden,
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cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."));
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namespace {
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class PHIElimination : public MachineFunctionPass {
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MachineRegisterInfo *MRI; // Machine register information
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LiveVariables *LV;
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LiveIntervals *LIS;
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public:
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static char ID; // Pass identification, replacement for typeid
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PHIElimination() : MachineFunctionPass(ID) {
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initializePHIEliminationPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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private:
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/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
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/// in predecessor basic blocks.
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bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
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void LowerPHINode(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator LastPHIIt);
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/// analyzePHINodes - Gather information about the PHI nodes in
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/// here. In particular, we want to map the number of uses of a virtual
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/// register which is used in a PHI node. We map that to the BB the
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/// vreg is coming from. This is used later to determine when the vreg
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/// is killed in the BB.
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void analyzePHINodes(const MachineFunction& MF);
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/// Split critical edges where necessary for good coalescer performance.
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bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineLoopInfo *MLI,
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std::vector<SparseBitVector<>> *LiveInSets);
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// These functions are temporary abstractions around LiveVariables and
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// LiveIntervals, so they can go away when LiveVariables does.
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bool isLiveIn(Register Reg, const MachineBasicBlock *MBB);
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bool isLiveOutPastPHIs(Register Reg, const MachineBasicBlock *MBB);
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using BBVRegPair = std::pair<unsigned, Register>;
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using VRegPHIUse = DenseMap<BBVRegPair, unsigned>;
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// Count the number of non-undef PHI uses of each register in each BB.
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VRegPHIUse VRegPHIUseCount;
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// Defs of PHI sources which are implicit_def.
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SmallPtrSet<MachineInstr*, 4> ImpDefs;
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// Map reusable lowered PHI node -> incoming join register.
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using LoweredPHIMap =
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DenseMap<MachineInstr*, unsigned, MachineInstrExpressionTrait>;
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LoweredPHIMap LoweredPHIs;
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};
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} // end anonymous namespace
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STATISTIC(NumLowered, "Number of phis lowered");
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STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
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STATISTIC(NumReused, "Number of reused lowered phis");
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char PHIElimination::ID = 0;
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char& llvm::PHIEliminationID = PHIElimination::ID;
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INITIALIZE_PASS_BEGIN(PHIElimination, DEBUG_TYPE,
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"Eliminate PHI nodes for register allocation",
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false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveVariables)
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INITIALIZE_PASS_END(PHIElimination, DEBUG_TYPE,
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"Eliminate PHI nodes for register allocation", false, false)
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void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addUsedIfAvailable<LiveVariables>();
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AU.addPreserved<LiveVariables>();
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AU.addPreserved<SlotIndexes>();
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AU.addPreserved<LiveIntervals>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addPreserved<MachineLoopInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
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MRI = &MF.getRegInfo();
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LV = getAnalysisIfAvailable<LiveVariables>();
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LIS = getAnalysisIfAvailable<LiveIntervals>();
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bool Changed = false;
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// Split critical edges to help the coalescer.
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if (!DisableEdgeSplitting && (LV || LIS)) {
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// A set of live-in regs for each MBB which is used to update LV
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// efficiently also with large functions.
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std::vector<SparseBitVector<>> LiveInSets;
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if (LV) {
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LiveInSets.resize(MF.size());
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for (unsigned Index = 0, e = MRI->getNumVirtRegs(); Index != e; ++Index) {
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// Set the bit for this register for each MBB where it is
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// live-through or live-in (killed).
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unsigned VirtReg = Register::index2VirtReg(Index);
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MachineInstr *DefMI = MRI->getVRegDef(VirtReg);
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if (!DefMI)
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continue;
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LiveVariables::VarInfo &VI = LV->getVarInfo(VirtReg);
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SparseBitVector<>::iterator AliveBlockItr = VI.AliveBlocks.begin();
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SparseBitVector<>::iterator EndItr = VI.AliveBlocks.end();
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while (AliveBlockItr != EndItr) {
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unsigned BlockNum = *(AliveBlockItr++);
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LiveInSets[BlockNum].set(Index);
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}
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// The register is live into an MBB in which it is killed but not
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// defined. See comment for VarInfo in LiveVariables.h.
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MachineBasicBlock *DefMBB = DefMI->getParent();
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if (VI.Kills.size() > 1 ||
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(!VI.Kills.empty() && VI.Kills.front()->getParent() != DefMBB))
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for (auto *MI : VI.Kills)
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LiveInSets[MI->getParent()->getNumber()].set(Index);
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}
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}
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MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
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for (auto &MBB : MF)
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Changed |= SplitPHIEdges(MF, MBB, MLI, (LV ? &LiveInSets : nullptr));
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}
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// This pass takes the function out of SSA form.
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MRI->leaveSSA();
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// Populate VRegPHIUseCount
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analyzePHINodes(MF);
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// Eliminate PHI instructions by inserting copies into predecessor blocks.
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for (auto &MBB : MF)
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Changed |= EliminatePHINodes(MF, MBB);
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// Remove dead IMPLICIT_DEF instructions.
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for (MachineInstr *DefMI : ImpDefs) {
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Register DefReg = DefMI->getOperand(0).getReg();
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if (MRI->use_nodbg_empty(DefReg)) {
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if (LIS)
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LIS->RemoveMachineInstrFromMaps(*DefMI);
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DefMI->eraseFromParent();
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}
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}
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// Clean up the lowered PHI instructions.
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for (auto &I : LoweredPHIs) {
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if (LIS)
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LIS->RemoveMachineInstrFromMaps(*I.first);
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MF.deleteMachineInstr(I.first);
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}
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// TODO: we should use the incremental DomTree updater here.
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if (Changed)
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if (auto *MDT = getAnalysisIfAvailable<MachineDominatorTree>())
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MDT->getBase().recalculate(MF);
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LoweredPHIs.clear();
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ImpDefs.clear();
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VRegPHIUseCount.clear();
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MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
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return Changed;
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}
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/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
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/// predecessor basic blocks.
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bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
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MachineBasicBlock &MBB) {
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if (MBB.empty() || !MBB.front().isPHI())
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return false; // Quick exit for basic blocks without PHIs.
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// Get an iterator to the last PHI node.
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MachineBasicBlock::iterator LastPHIIt =
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std::prev(MBB.SkipPHIsAndLabels(MBB.begin()));
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while (MBB.front().isPHI())
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LowerPHINode(MBB, LastPHIIt);
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return true;
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}
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/// Return true if all defs of VirtReg are implicit-defs.
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/// This includes registers with no defs.
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static bool isImplicitlyDefined(unsigned VirtReg,
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const MachineRegisterInfo &MRI) {
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for (MachineInstr &DI : MRI.def_instructions(VirtReg))
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if (!DI.isImplicitDef())
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return false;
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return true;
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}
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/// Return true if all sources of the phi node are implicit_def's, or undef's.
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static bool allPhiOperandsUndefined(const MachineInstr &MPhi,
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const MachineRegisterInfo &MRI) {
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for (unsigned I = 1, E = MPhi.getNumOperands(); I != E; I += 2) {
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const MachineOperand &MO = MPhi.getOperand(I);
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if (!isImplicitlyDefined(MO.getReg(), MRI) && !MO.isUndef())
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return false;
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}
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return true;
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}
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/// LowerPHINode - Lower the PHI node at the top of the specified block.
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void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator LastPHIIt) {
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++NumLowered;
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MachineBasicBlock::iterator AfterPHIsIt = std::next(LastPHIIt);
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// Unlink the PHI node from the basic block, but don't delete the PHI yet.
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MachineInstr *MPhi = MBB.remove(&*MBB.begin());
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unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
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Register DestReg = MPhi->getOperand(0).getReg();
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assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
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bool isDead = MPhi->getOperand(0).isDead();
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// Create a new register for the incoming PHI arguments.
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MachineFunction &MF = *MBB.getParent();
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unsigned IncomingReg = 0;
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bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
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// Insert a register to register copy at the top of the current block (but
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// after any remaining phi nodes) which copies the new incoming register
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// into the phi node destination.
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MachineInstr *PHICopy = nullptr;
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const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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if (allPhiOperandsUndefined(*MPhi, *MRI))
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// If all sources of a PHI node are implicit_def or undef uses, just emit an
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// implicit_def instead of a copy.
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PHICopy = BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
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TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
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else {
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// Can we reuse an earlier PHI node? This only happens for critical edges,
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// typically those created by tail duplication.
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unsigned &entry = LoweredPHIs[MPhi];
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if (entry) {
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// An identical PHI node was already lowered. Reuse the incoming register.
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IncomingReg = entry;
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reusedIncoming = true;
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++NumReused;
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LLVM_DEBUG(dbgs() << "Reusing " << printReg(IncomingReg) << " for "
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<< *MPhi);
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} else {
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const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
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entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
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}
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// Give the target possiblity to handle special cases fallthrough otherwise
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PHICopy = TII->createPHIDestinationCopy(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
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IncomingReg, DestReg);
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}
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if (MPhi->peekDebugInstrNum()) {
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// If referred to by debug-info, store where this PHI was.
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MachineFunction *MF = MBB.getParent();
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unsigned ID = MPhi->peekDebugInstrNum();
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auto P = MachineFunction::DebugPHIRegallocPos(&MBB, IncomingReg, 0);
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auto Res = MF->DebugPHIPositions.insert({ID, P});
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assert(Res.second);
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(void)Res;
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}
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// Update live variable information if there is any.
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if (LV) {
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if (IncomingReg) {
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LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
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// Increment use count of the newly created virtual register.
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LV->setPHIJoin(IncomingReg);
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MachineInstr *OldKill = nullptr;
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bool IsPHICopyAfterOldKill = false;
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if (reusedIncoming && (OldKill = VI.findKill(&MBB))) {
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// Calculate whether the PHICopy is after the OldKill.
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// In general, the PHICopy is inserted as the first non-phi instruction
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// by default, so it's before the OldKill. But some Target hooks for
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// createPHIDestinationCopy() may modify the default insert position of
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// PHICopy.
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for (auto I = MBB.SkipPHIsAndLabels(MBB.begin()), E = MBB.end();
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I != E; ++I) {
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if (I == PHICopy)
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break;
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if (I == OldKill) {
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IsPHICopyAfterOldKill = true;
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break;
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}
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}
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}
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// When we are reusing the incoming register and it has been marked killed
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// by OldKill, if the PHICopy is after the OldKill, we should remove the
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// killed flag from OldKill.
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if (IsPHICopyAfterOldKill) {
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LLVM_DEBUG(dbgs() << "Remove old kill from " << *OldKill);
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LV->removeVirtualRegisterKilled(IncomingReg, *OldKill);
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LLVM_DEBUG(MBB.dump());
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}
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// Add information to LiveVariables to know that the first used incoming
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// value or the resued incoming value whose PHICopy is after the OldKIll
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// is killed. Note that because the value is defined in several places
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// (once each for each incoming block), the "def" block and instruction
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// fields for the VarInfo is not filled in.
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if (!OldKill || IsPHICopyAfterOldKill)
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LV->addVirtualRegisterKilled(IncomingReg, *PHICopy);
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}
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// Since we are going to be deleting the PHI node, if it is the last use of
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// any registers, or if the value itself is dead, we need to move this
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// information over to the new copy we just inserted.
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LV->removeVirtualRegistersKilled(*MPhi);
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// If the result is dead, update LV.
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if (isDead) {
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LV->addVirtualRegisterDead(DestReg, *PHICopy);
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LV->removeVirtualRegisterDead(DestReg, *MPhi);
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}
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}
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// Update LiveIntervals for the new copy or implicit def.
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if (LIS) {
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SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(*PHICopy);
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SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
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if (IncomingReg) {
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// Add the region from the beginning of MBB to the copy instruction to
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// IncomingReg's live interval.
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LiveInterval &IncomingLI = LIS->createEmptyInterval(IncomingReg);
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VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex);
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if (!IncomingVNI)
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IncomingVNI = IncomingLI.getNextValue(MBBStartIndex,
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LIS->getVNInfoAllocator());
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IncomingLI.addSegment(LiveInterval::Segment(MBBStartIndex,
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DestCopyIndex.getRegSlot(),
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IncomingVNI));
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}
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LiveInterval &DestLI = LIS->getInterval(DestReg);
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assert(!DestLI.empty() && "PHIs should have nonempty LiveIntervals.");
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if (DestLI.endIndex().isDead()) {
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// A dead PHI's live range begins and ends at the start of the MBB, but
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// the lowered copy, which will still be dead, needs to begin and end at
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// the copy instruction.
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VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex);
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assert(OrigDestVNI && "PHI destination should be live at block entry.");
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DestLI.removeSegment(MBBStartIndex, MBBStartIndex.getDeadSlot());
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DestLI.createDeadDef(DestCopyIndex.getRegSlot(),
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LIS->getVNInfoAllocator());
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DestLI.removeValNo(OrigDestVNI);
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} else {
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// Otherwise, remove the region from the beginning of MBB to the copy
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// instruction from DestReg's live interval.
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DestLI.removeSegment(MBBStartIndex, DestCopyIndex.getRegSlot());
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VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
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assert(DestVNI && "PHI destination should be live at its definition.");
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DestVNI->def = DestCopyIndex.getRegSlot();
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}
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}
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// Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
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for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
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if (!MPhi->getOperand(i).isUndef()) {
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--VRegPHIUseCount[BBVRegPair(
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MPhi->getOperand(i + 1).getMBB()->getNumber(),
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MPhi->getOperand(i).getReg())];
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}
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}
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// Now loop over all of the incoming arguments, changing them to copy into the
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// IncomingReg register in the corresponding predecessor basic block.
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SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
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for (int i = NumSrcs - 1; i >= 0; --i) {
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Register SrcReg = MPhi->getOperand(i * 2 + 1).getReg();
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unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
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bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
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isImplicitlyDefined(SrcReg, *MRI);
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assert(Register::isVirtualRegister(SrcReg) &&
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"Machine PHI Operands must all be virtual registers!");
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// Get the MachineBasicBlock equivalent of the BasicBlock that is the source
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// path the PHI.
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MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
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// Check to make sure we haven't already emitted the copy for this block.
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// This can happen because PHI nodes may have multiple entries for the same
|
|
// basic block.
|
|
if (!MBBsInsertedInto.insert(&opBlock).second)
|
|
continue; // If the copy has already been emitted, we're done.
|
|
|
|
MachineInstr *SrcRegDef = MRI->getVRegDef(SrcReg);
|
|
if (SrcRegDef && TII->isUnspillableTerminator(SrcRegDef)) {
|
|
assert(SrcRegDef->getOperand(0).isReg() &&
|
|
SrcRegDef->getOperand(0).isDef() &&
|
|
"Expected operand 0 to be a reg def!");
|
|
// Now that the PHI's use has been removed (as the instruction was
|
|
// removed) there should be no other uses of the SrcReg.
|
|
assert(MRI->use_empty(SrcReg) &&
|
|
"Expected a single use from UnspillableTerminator");
|
|
SrcRegDef->getOperand(0).setReg(IncomingReg);
|
|
|
|
// Update LiveVariables.
|
|
if (LV) {
|
|
LiveVariables::VarInfo &SrcVI = LV->getVarInfo(SrcReg);
|
|
LiveVariables::VarInfo &IncomingVI = LV->getVarInfo(IncomingReg);
|
|
IncomingVI.AliveBlocks = std::move(SrcVI.AliveBlocks);
|
|
SrcVI.AliveBlocks.clear();
|
|
}
|
|
|
|
continue;
|
|
}
|
|
|
|
// Find a safe location to insert the copy, this may be the first terminator
|
|
// in the block (or end()).
|
|
MachineBasicBlock::iterator InsertPos =
|
|
findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
|
|
|
|
// Insert the copy.
|
|
MachineInstr *NewSrcInstr = nullptr;
|
|
if (!reusedIncoming && IncomingReg) {
|
|
if (SrcUndef) {
|
|
// The source register is undefined, so there is no need for a real
|
|
// COPY, but we still need to ensure joint dominance by defs.
|
|
// Insert an IMPLICIT_DEF instruction.
|
|
NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
|
|
TII->get(TargetOpcode::IMPLICIT_DEF),
|
|
IncomingReg);
|
|
|
|
// Clean up the old implicit-def, if there even was one.
|
|
if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
|
|
if (DefMI->isImplicitDef())
|
|
ImpDefs.insert(DefMI);
|
|
} else {
|
|
// Delete the debug location, since the copy is inserted into a
|
|
// different basic block.
|
|
NewSrcInstr = TII->createPHISourceCopy(opBlock, InsertPos, nullptr,
|
|
SrcReg, SrcSubReg, IncomingReg);
|
|
}
|
|
}
|
|
|
|
// We only need to update the LiveVariables kill of SrcReg if this was the
|
|
// last PHI use of SrcReg to be lowered on this CFG edge and it is not live
|
|
// out of the predecessor. We can also ignore undef sources.
|
|
if (LV && !SrcUndef &&
|
|
!VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
|
|
!LV->isLiveOut(SrcReg, opBlock)) {
|
|
// We want to be able to insert a kill of the register if this PHI (aka,
|
|
// the copy we just inserted) is the last use of the source value. Live
|
|
// variable analysis conservatively handles this by saying that the value
|
|
// is live until the end of the block the PHI entry lives in. If the value
|
|
// really is dead at the PHI copy, there will be no successor blocks which
|
|
// have the value live-in.
|
|
|
|
// Okay, if we now know that the value is not live out of the block, we
|
|
// can add a kill marker in this block saying that it kills the incoming
|
|
// value!
|
|
|
|
// In our final twist, we have to decide which instruction kills the
|
|
// register. In most cases this is the copy, however, terminator
|
|
// instructions at the end of the block may also use the value. In this
|
|
// case, we should mark the last such terminator as being the killing
|
|
// block, not the copy.
|
|
MachineBasicBlock::iterator KillInst = opBlock.end();
|
|
for (MachineBasicBlock::iterator Term = InsertPos; Term != opBlock.end();
|
|
++Term) {
|
|
if (Term->readsRegister(SrcReg))
|
|
KillInst = Term;
|
|
}
|
|
|
|
if (KillInst == opBlock.end()) {
|
|
// No terminator uses the register.
|
|
|
|
if (reusedIncoming || !IncomingReg) {
|
|
// We may have to rewind a bit if we didn't insert a copy this time.
|
|
KillInst = InsertPos;
|
|
while (KillInst != opBlock.begin()) {
|
|
--KillInst;
|
|
if (KillInst->isDebugInstr())
|
|
continue;
|
|
if (KillInst->readsRegister(SrcReg))
|
|
break;
|
|
}
|
|
} else {
|
|
// We just inserted this copy.
|
|
KillInst = NewSrcInstr;
|
|
}
|
|
}
|
|
assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
|
|
|
|
// Finally, mark it killed.
|
|
LV->addVirtualRegisterKilled(SrcReg, *KillInst);
|
|
|
|
// This vreg no longer lives all of the way through opBlock.
|
|
unsigned opBlockNum = opBlock.getNumber();
|
|
LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
|
|
}
|
|
|
|
if (LIS) {
|
|
if (NewSrcInstr) {
|
|
LIS->InsertMachineInstrInMaps(*NewSrcInstr);
|
|
LIS->addSegmentToEndOfBlock(IncomingReg, *NewSrcInstr);
|
|
}
|
|
|
|
if (!SrcUndef &&
|
|
!VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {
|
|
LiveInterval &SrcLI = LIS->getInterval(SrcReg);
|
|
|
|
bool isLiveOut = false;
|
|
for (MachineBasicBlock *Succ : opBlock.successors()) {
|
|
SlotIndex startIdx = LIS->getMBBStartIdx(Succ);
|
|
VNInfo *VNI = SrcLI.getVNInfoAt(startIdx);
|
|
|
|
// Definitions by other PHIs are not truly live-in for our purposes.
|
|
if (VNI && VNI->def != startIdx) {
|
|
isLiveOut = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!isLiveOut) {
|
|
MachineBasicBlock::iterator KillInst = opBlock.end();
|
|
for (MachineBasicBlock::iterator Term = InsertPos;
|
|
Term != opBlock.end(); ++Term) {
|
|
if (Term->readsRegister(SrcReg))
|
|
KillInst = Term;
|
|
}
|
|
|
|
if (KillInst == opBlock.end()) {
|
|
// No terminator uses the register.
|
|
|
|
if (reusedIncoming || !IncomingReg) {
|
|
// We may have to rewind a bit if we didn't just insert a copy.
|
|
KillInst = InsertPos;
|
|
while (KillInst != opBlock.begin()) {
|
|
--KillInst;
|
|
if (KillInst->isDebugInstr())
|
|
continue;
|
|
if (KillInst->readsRegister(SrcReg))
|
|
break;
|
|
}
|
|
} else {
|
|
// We just inserted this copy.
|
|
KillInst = std::prev(InsertPos);
|
|
}
|
|
}
|
|
assert(KillInst->readsRegister(SrcReg) &&
|
|
"Cannot find kill instruction");
|
|
|
|
SlotIndex LastUseIndex = LIS->getInstructionIndex(*KillInst);
|
|
SrcLI.removeSegment(LastUseIndex.getRegSlot(),
|
|
LIS->getMBBEndIdx(&opBlock));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
|
|
if (reusedIncoming || !IncomingReg) {
|
|
if (LIS)
|
|
LIS->RemoveMachineInstrFromMaps(*MPhi);
|
|
MF.deleteMachineInstr(MPhi);
|
|
}
|
|
}
|
|
|
|
/// analyzePHINodes - Gather information about the PHI nodes in here. In
|
|
/// particular, we want to map the number of uses of a virtual register which is
|
|
/// used in a PHI node. We map that to the BB the vreg is coming from. This is
|
|
/// used later to determine when the vreg is killed in the BB.
|
|
void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
|
|
for (const auto &MBB : MF) {
|
|
for (const auto &BBI : MBB) {
|
|
if (!BBI.isPHI())
|
|
break;
|
|
for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2) {
|
|
if (!BBI.getOperand(i).isUndef()) {
|
|
++VRegPHIUseCount[BBVRegPair(
|
|
BBI.getOperand(i + 1).getMBB()->getNumber(),
|
|
BBI.getOperand(i).getReg())];
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
|
|
MachineBasicBlock &MBB,
|
|
MachineLoopInfo *MLI,
|
|
std::vector<SparseBitVector<>> *LiveInSets) {
|
|
if (MBB.empty() || !MBB.front().isPHI() || MBB.isEHPad())
|
|
return false; // Quick exit for basic blocks without PHIs.
|
|
|
|
const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : nullptr;
|
|
bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();
|
|
|
|
bool Changed = false;
|
|
for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
|
|
BBI != BBE && BBI->isPHI(); ++BBI) {
|
|
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
|
|
Register Reg = BBI->getOperand(i).getReg();
|
|
MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
|
|
// Is there a critical edge from PreMBB to MBB?
|
|
if (PreMBB->succ_size() == 1)
|
|
continue;
|
|
|
|
// Avoid splitting backedges of loops. It would introduce small
|
|
// out-of-line blocks into the loop which is very bad for code placement.
|
|
if (PreMBB == &MBB && !SplitAllCriticalEdges)
|
|
continue;
|
|
const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : nullptr;
|
|
if (IsLoopHeader && PreLoop == CurLoop && !SplitAllCriticalEdges)
|
|
continue;
|
|
|
|
// LV doesn't consider a phi use live-out, so isLiveOut only returns true
|
|
// when the source register is live-out for some other reason than a phi
|
|
// use. That means the copy we will insert in PreMBB won't be a kill, and
|
|
// there is a risk it may not be coalesced away.
|
|
//
|
|
// If the copy would be a kill, there is no need to split the edge.
|
|
bool ShouldSplit = isLiveOutPastPHIs(Reg, PreMBB);
|
|
if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit)
|
|
continue;
|
|
if (ShouldSplit) {
|
|
LLVM_DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge "
|
|
<< printMBBReference(*PreMBB) << " -> "
|
|
<< printMBBReference(MBB) << ": " << *BBI);
|
|
}
|
|
|
|
// If Reg is not live-in to MBB, it means it must be live-in to some
|
|
// other PreMBB successor, and we can avoid the interference by splitting
|
|
// the edge.
|
|
//
|
|
// If Reg *is* live-in to MBB, the interference is inevitable and a copy
|
|
// is likely to be left after coalescing. If we are looking at a loop
|
|
// exiting edge, split it so we won't insert code in the loop, otherwise
|
|
// don't bother.
|
|
ShouldSplit = ShouldSplit && !isLiveIn(Reg, &MBB);
|
|
|
|
// Check for a loop exiting edge.
|
|
if (!ShouldSplit && CurLoop != PreLoop) {
|
|
LLVM_DEBUG({
|
|
dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
|
|
if (PreLoop)
|
|
dbgs() << "PreLoop: " << *PreLoop;
|
|
if (CurLoop)
|
|
dbgs() << "CurLoop: " << *CurLoop;
|
|
});
|
|
// This edge could be entering a loop, exiting a loop, or it could be
|
|
// both: Jumping directly form one loop to the header of a sibling
|
|
// loop.
|
|
// Split unless this edge is entering CurLoop from an outer loop.
|
|
ShouldSplit = PreLoop && !PreLoop->contains(CurLoop);
|
|
}
|
|
if (!ShouldSplit && !SplitAllCriticalEdges)
|
|
continue;
|
|
if (!PreMBB->SplitCriticalEdge(&MBB, *this, LiveInSets)) {
|
|
LLVM_DEBUG(dbgs() << "Failed to split critical edge.\n");
|
|
continue;
|
|
}
|
|
Changed = true;
|
|
++NumCriticalEdgesSplit;
|
|
}
|
|
}
|
|
return Changed;
|
|
}
|
|
|
|
bool PHIElimination::isLiveIn(Register Reg, const MachineBasicBlock *MBB) {
|
|
assert((LV || LIS) &&
|
|
"isLiveIn() requires either LiveVariables or LiveIntervals");
|
|
if (LIS)
|
|
return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
|
|
else
|
|
return LV->isLiveIn(Reg, *MBB);
|
|
}
|
|
|
|
bool PHIElimination::isLiveOutPastPHIs(Register Reg,
|
|
const MachineBasicBlock *MBB) {
|
|
assert((LV || LIS) &&
|
|
"isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
|
|
// LiveVariables considers uses in PHIs to be in the predecessor basic block,
|
|
// so that a register used only in a PHI is not live out of the block. In
|
|
// contrast, LiveIntervals considers uses in PHIs to be on the edge rather than
|
|
// in the predecessor basic block, so that a register used only in a PHI is live
|
|
// out of the block.
|
|
if (LIS) {
|
|
const LiveInterval &LI = LIS->getInterval(Reg);
|
|
for (const MachineBasicBlock *SI : MBB->successors())
|
|
if (LI.liveAt(LIS->getMBBStartIdx(SI)))
|
|
return true;
|
|
return false;
|
|
} else {
|
|
return LV->isLiveOut(Reg, *MBB);
|
|
}
|
|
}
|