forked from OSchip/llvm-project
216 lines
7.1 KiB
C++
216 lines
7.1 KiB
C++
//===- MachineLoopInfo.cpp - Natural Loop Calculator ----------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the MachineLoopInfo class that is used to identify natural
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// loops and determine the loop depth of various nodes of the CFG. Note that
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// the loops identified may actually be several natural loops that share the
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// same header node... not just a single natural loop.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/Analysis/LoopInfoImpl.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Config/llvm-config.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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// Explicitly instantiate methods in LoopInfoImpl.h for MI-level Loops.
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template class llvm::LoopBase<MachineBasicBlock, MachineLoop>;
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template class llvm::LoopInfoBase<MachineBasicBlock, MachineLoop>;
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char MachineLoopInfo::ID = 0;
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MachineLoopInfo::MachineLoopInfo() : MachineFunctionPass(ID) {
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initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
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}
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INITIALIZE_PASS_BEGIN(MachineLoopInfo, "machine-loops",
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"Machine Natural Loop Construction", true, true)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_END(MachineLoopInfo, "machine-loops",
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"Machine Natural Loop Construction", true, true)
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char &llvm::MachineLoopInfoID = MachineLoopInfo::ID;
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bool MachineLoopInfo::runOnMachineFunction(MachineFunction &) {
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calculate(getAnalysis<MachineDominatorTree>());
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return false;
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}
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void MachineLoopInfo::calculate(MachineDominatorTree &MDT) {
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releaseMemory();
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LI.analyze(MDT.getBase());
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}
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void MachineLoopInfo::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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AU.addRequired<MachineDominatorTree>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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MachineBasicBlock *MachineLoop::getTopBlock() {
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MachineBasicBlock *TopMBB = getHeader();
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MachineFunction::iterator Begin = TopMBB->getParent()->begin();
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if (TopMBB->getIterator() != Begin) {
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MachineBasicBlock *PriorMBB = &*std::prev(TopMBB->getIterator());
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while (contains(PriorMBB)) {
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TopMBB = PriorMBB;
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if (TopMBB->getIterator() == Begin)
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break;
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PriorMBB = &*std::prev(TopMBB->getIterator());
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}
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}
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return TopMBB;
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}
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MachineBasicBlock *MachineLoop::getBottomBlock() {
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MachineBasicBlock *BotMBB = getHeader();
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MachineFunction::iterator End = BotMBB->getParent()->end();
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if (BotMBB->getIterator() != std::prev(End)) {
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MachineBasicBlock *NextMBB = &*std::next(BotMBB->getIterator());
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while (contains(NextMBB)) {
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BotMBB = NextMBB;
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if (BotMBB == &*std::next(BotMBB->getIterator()))
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break;
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NextMBB = &*std::next(BotMBB->getIterator());
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}
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}
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return BotMBB;
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}
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MachineBasicBlock *MachineLoop::findLoopControlBlock() {
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if (MachineBasicBlock *Latch = getLoopLatch()) {
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if (isLoopExiting(Latch))
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return Latch;
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else
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return getExitingBlock();
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}
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return nullptr;
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}
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DebugLoc MachineLoop::getStartLoc() const {
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// Try the pre-header first.
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if (MachineBasicBlock *PHeadMBB = getLoopPreheader())
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if (const BasicBlock *PHeadBB = PHeadMBB->getBasicBlock())
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if (DebugLoc DL = PHeadBB->getTerminator()->getDebugLoc())
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return DL;
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// If we have no pre-header or there are no instructions with debug
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// info in it, try the header.
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if (MachineBasicBlock *HeadMBB = getHeader())
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if (const BasicBlock *HeadBB = HeadMBB->getBasicBlock())
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return HeadBB->getTerminator()->getDebugLoc();
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return DebugLoc();
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}
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MachineBasicBlock *
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MachineLoopInfo::findLoopPreheader(MachineLoop *L, bool SpeculativePreheader,
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bool FindMultiLoopPreheader) const {
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if (MachineBasicBlock *PB = L->getLoopPreheader())
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return PB;
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if (!SpeculativePreheader)
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return nullptr;
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MachineBasicBlock *HB = L->getHeader(), *LB = L->getLoopLatch();
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if (HB->pred_size() != 2 || HB->hasAddressTaken())
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return nullptr;
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// Find the predecessor of the header that is not the latch block.
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MachineBasicBlock *Preheader = nullptr;
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for (MachineBasicBlock *P : HB->predecessors()) {
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if (P == LB)
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continue;
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// Sanity.
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if (Preheader)
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return nullptr;
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Preheader = P;
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}
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// Check if the preheader candidate is a successor of any other loop
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// headers. We want to avoid having two loop setups in the same block.
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if (!FindMultiLoopPreheader) {
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for (MachineBasicBlock *S : Preheader->successors()) {
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if (S == HB)
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continue;
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MachineLoop *T = getLoopFor(S);
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if (T && T->getHeader() == S)
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return nullptr;
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}
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}
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return Preheader;
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}
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bool MachineLoop::isLoopInvariant(MachineInstr &I) const {
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MachineFunction *MF = I.getParent()->getParent();
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MachineRegisterInfo *MRI = &MF->getRegInfo();
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const TargetSubtargetInfo &ST = MF->getSubtarget();
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const TargetRegisterInfo *TRI = ST.getRegisterInfo();
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const TargetInstrInfo *TII = ST.getInstrInfo();
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// The instruction is loop invariant if all of its operands are.
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for (const MachineOperand &MO : I.operands()) {
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if (!MO.isReg())
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continue;
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Register Reg = MO.getReg();
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if (Reg == 0) continue;
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// An instruction that uses or defines a physical register can't e.g. be
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// hoisted, so mark this as not invariant.
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if (Register::isPhysicalRegister(Reg)) {
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if (MO.isUse()) {
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// If the physreg has no defs anywhere, it's just an ambient register
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// and we can freely move its uses. Alternatively, if it's allocatable,
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// it could get allocated to something with a def during allocation.
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// However, if the physreg is known to always be caller saved/restored
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// then this use is safe to hoist.
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if (!MRI->isConstantPhysReg(Reg) &&
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!(TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *I.getMF())) &&
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!TII->isIgnorableUse(MO))
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return false;
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// Otherwise it's safe to move.
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continue;
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} else if (!MO.isDead()) {
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// A def that isn't dead can't be moved.
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return false;
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} else if (getHeader()->isLiveIn(Reg)) {
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// If the reg is live into the loop, we can't hoist an instruction
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// which would clobber it.
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return false;
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}
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}
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if (!MO.isUse())
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continue;
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assert(MRI->getVRegDef(Reg) &&
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"Machine instr not mapped for this vreg?!");
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// If the loop contains the definition of an operand, then the instruction
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// isn't loop invariant.
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if (contains(MRI->getVRegDef(Reg)))
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return false;
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}
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// If we got this far, the instruction is loop invariant!
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return true;
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}
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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LLVM_DUMP_METHOD void MachineLoop::dump() const {
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print(dbgs());
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}
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#endif
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