llvm-project/llvm/lib/CodeGen
Craig Topper 1bf4bbc492 [LegalizeTypes][RISCV][WebAssembly] Expand ABS in PromoteIntRes_ABS if it will expand to sra+xor+sub later.
If we promote the ABS and then Expand in LegalizeDAG, then both the
sra and the xor will have their inputs sign extended. This generates
extra code on RISCV which lacks an i8 or i16 sign extend instructon.
If we expand during type legalization, then only the sra will get its
input sign extended. RISCV is able to combine this with the sra by
doing a shift left followed by an sra.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D121664
2022-03-15 08:27:39 -07:00
..
AsmPrinter [DebugInfo] Include DW_TAG_skeleton_unit when looking for parent UnitDie 2022-03-12 13:27:42 -08:00
GlobalISel [GlobalISel] Fix store merging incorrectly merging volatile stores. 2022-03-14 13:48:51 -07:00
LiveDebugValues Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MIRParser Cleanup includes: DebugInfo & CodeGen 2022-03-12 17:26:40 +01:00
SelectionDAG [LegalizeTypes][RISCV][WebAssembly] Expand ABS in PromoteIntRes_ABS if it will expand to sra+xor+sub later. 2022-03-15 08:27:39 -07:00
AggressiveAntiDepBreaker.cpp [llvm] Remove redundant member initialization (NFC) 2022-01-07 17:45:09 -08:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
AllocationOrder.h
Analysis.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
AtomicExpandPass.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
BasicBlockSections.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
BasicTargetTransformInfo.cpp
BranchFolding.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
BranchFolding.h Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
BranchRelaxation.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
BreakFalseDeps.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
CFGuardLongjmp.cpp
CFIInstrInserter.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
CMakeLists.txt [nfc][codegen] Move RegisterBank[Info].cpp under CodeGen 2022-02-15 11:27:15 -08:00
CalcSpillWeights.cpp [NFC] Expose isRematerializable and copyHint from CalcSpillWeights 2022-01-04 08:11:49 -08:00
CallingConvLower.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
CodeGen.cpp Revert rG9c542a5a4e1ba36c24e48185712779df52b7f7a6 "Lower `@llvm.global_dtors` using `__cxa_atexit` on MachO" 2022-03-15 13:01:35 +00:00
CodeGenCommonISel.cpp Reapply: StackProtector: ignore debug insts when splitting blocks. 2022-02-14 10:58:22 +00:00
CodeGenPassBuilder.cpp
CodeGenPrepare.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
CommandFlags.cpp Revert rG9c542a5a4e1ba36c24e48185712779df52b7f7a6 "Lower `@llvm.global_dtors` using `__cxa_atexit` on MachO" 2022-03-15 13:01:35 +00:00
CriticalAntiDepBreaker.cpp [llvm] Remove redundant member initialization (NFC) 2022-01-07 17:45:09 -08:00
CriticalAntiDepBreaker.h
DFAPacketizer.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
DeadMachineInstructionElim.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
DetectDeadLanes.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
DwarfEHPrepare.cpp Reland "[ARM] __cxa_end_cleanup should be called instead of _UnwindResume." 2021-10-28 21:45:09 +02:00
EHContGuardCatchret.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
EarlyIfConversion.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
EdgeBundles.cpp
ExecutionDomainFix.cpp
ExpandMemCmp.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
ExpandPostRAPseudos.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
ExpandReductions.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
ExpandVectorPredication.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
FEntryInserter.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
FaultMaps.cpp
FinalizeISel.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
FixupStatepointCallerSaved.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
FuncletLayout.cpp
GCMetadata.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
GCMetadataPrinter.cpp
GCRootLowering.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
GlobalMerge.cpp [llvm] Use range-based for loops (NFC) 2021-11-28 18:14:49 -08:00
HardwareLoops.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
IfConversion.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
ImplicitNullChecks.cpp [llvm] Use none_of instead of \!any_of (NFC) 2021-12-17 13:48:57 -08:00
IndirectBrExpandPass.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
InlineSpiller.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
InterferenceCache.cpp [CodeGen] Use range-based for loops (NFC) 2021-12-03 20:45:59 -08:00
InterferenceCache.h [CodeGen] Use = default (NFC) 2022-02-06 10:54:44 -08:00
InterleavedAccessPass.cpp Cleanup includes: DebugInfo & CodeGen 2022-03-12 17:26:40 +01:00
InterleavedLoadCombinePass.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
IntrinsicLowering.cpp [Analysis, CodeGen] Migrate from arg_operands to args (NFC) 2021-10-03 08:22:20 -07:00
JMCInstrumenter.cpp [JMCInstrument] infer proper path style based on debug info 2022-03-10 10:50:44 -08:00
LLVMTargetMachine.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
LatencyPriorityQueue.cpp [llvm] Use range-based for loops (NFC) 2021-11-28 18:14:49 -08:00
LazyMachineBlockFrequencyInfo.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
LexicalScopes.cpp
LiveDebugVariables.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
LiveDebugVariables.h [GlobalISel] Allow DBG_VALUE to use undefined vregs before LiveDebugValues. 2021-12-05 15:55:59 -05:00
LiveInterval.cpp [CodeGen] Tweak whitespace in LiveInterval printing 2021-11-11 15:19:32 +00:00
LiveIntervalCalc.cpp Cleanup includes: DebugInfo & CodeGen 2022-03-12 17:26:40 +01:00
LiveIntervalUnion.cpp [nfc][regalloc] const LiveIntervals within the allocator 2022-02-03 12:35:36 -08:00
LiveIntervals.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
LivePhysRegs.cpp [llvm] Use llvm::reverse (NFC) 2021-11-06 19:31:18 -07:00
LiveRangeCalc.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
LiveRangeEdit.cpp Check subrange liveness at rematerialization 2021-12-13 11:11:55 -08:00
LiveRangeShrink.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
LiveRangeUtils.h [NFC][llvm] Inclusive language: remove instance of master in LiveRangeUtils.h 2021-11-23 13:07:42 -06:00
LiveRegMatrix.cpp [nfc][regalloc] const LiveIntervals within the allocator 2022-02-03 12:35:36 -08:00
LiveRegUnits.cpp
LiveStacks.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
LiveVariables.cpp [CodeGen] Use range-based for loops (NFC) 2021-12-03 20:45:59 -08:00
LocalStackSlotAllocation.cpp [CodeGen] Return better Changed status from LocalStackSlotAllocation 2022-02-17 09:31:41 +00:00
LoopTraversal.cpp [llvm] Use pop_back_val (NFC) 2021-09-19 13:44:23 -07:00
LowLevelType.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
LowerEmuTLS.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MBFIWrapper.cpp
MIRCanonicalizerPass.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MIRFSDiscriminator.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MIRNamerPass.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MIRPrinter.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MIRPrintingPass.cpp
MIRSampleProfile.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MIRVRegNamerUtils.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MIRVRegNamerUtils.h
MIRYamlMapping.cpp
MLRegallocEvictAdvisor.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineBasicBlock.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineBlockFrequencyInfo.cpp
MachineBlockPlacement.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineBranchProbabilityInfo.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineCSE.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineCheckDebugify.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineCombiner.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineCopyPropagation.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineCycleAnalysis.cpp Reapply CycleInfo: Introduce cycles as a generalization of loops 2021-12-10 14:36:43 +05:30
MachineDebugify.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineDominanceFrontier.cpp Cleanup includes: DebugInfo & CodeGen 2022-03-12 17:26:40 +01:00
MachineDominators.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineFrameInfo.cpp
MachineFunction.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineFunctionPass.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineFunctionPrinterPass.cpp
MachineFunctionSplitter.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineInstr.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineInstrBundle.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineLICM.cpp [MachineLICM] Simplify code and avoid adding nullptr values to ParentMap. NFC 2022-03-15 01:24:01 -07:00
MachineLoopInfo.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineLoopUtils.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineModuleInfo.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineModuleInfoImpls.cpp
MachineModuleSlotTracker.cpp [CodeGen] Use default member initialization (NFC) 2022-01-30 12:32:51 -08:00
MachineOperand.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineOptimizationRemarkEmitter.cpp [llvm] Remove redundant member initialization (NFC) 2022-01-07 17:45:09 -08:00
MachineOutliner.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachinePassManager.cpp
MachinePipeliner.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachinePostDominators.cpp
MachineRegionInfo.cpp Revert "[NFC] Remove LinkAll*.h" 2021-11-02 09:08:09 -07:00
MachineRegisterInfo.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineSSAContext.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineSSAUpdater.cpp [DebugInfo] Attempt to preserve more information during tail duplication 2021-12-03 15:30:05 +00:00
MachineScheduler.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineSink.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineSizeOpts.cpp [NFC] Use Optional<ProfileCount> to model invalid counts 2021-11-14 19:03:30 -08:00
MachineStableHash.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineStripDebug.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MachineTraceMetrics.cpp [llvm] Use llvm::reverse (NFC) 2021-12-12 16:13:49 -08:00
MachineVerifier.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MacroFusion.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
ModuloSchedule.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
MultiHazardRecognizer.cpp
NonRelocatableStringpool.cpp Move STLFunctionalExtras out of STLExtras 2022-01-24 14:13:21 +01:00
OptimizePHIs.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
PHIElimination.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
ParallelCG.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
PatchableFunction.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
PeepholeOptimizer.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
PostRAHazardRecognizer.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
PostRASchedulerList.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
PreISelIntrinsicLowering.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
ProcessImplicitDefs.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
PrologEpilogInserter.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
PseudoProbeInserter.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
PseudoSourceValue.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
RDFGraph.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
RDFLiveness.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
RDFRegisters.cpp
README.txt
ReachingDefAnalysis.cpp Use RegisterInfo::regsOverlaps instead of checking aliases 2022-02-26 20:32:12 +01:00
RegAllocBase.cpp [nfc][regalloc] const LiveIntervals within the allocator 2022-02-03 12:35:36 -08:00
RegAllocBase.h [nfc][regalloc] const LiveIntervals within the allocator 2022-02-03 12:35:36 -08:00
RegAllocBasic.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
RegAllocEvictionAdvisor.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
RegAllocEvictionAdvisor.h Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
RegAllocFast.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
RegAllocGreedy.cpp [CodeGen] Remove an unused variable introduced in D121128 2022-03-14 11:41:04 -07:00
RegAllocGreedy.h [regalloc] Remove -consider-local-interval-cost 2022-03-14 10:49:16 -07:00
RegAllocPBQP.cpp [CodeGen] Use range-based for loops (NFC) 2021-12-04 08:48:05 -08:00
RegAllocScore.cpp Cleanup includes: DebugInfo & CodeGen 2022-03-12 17:26:40 +01:00
RegAllocScore.h Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
RegUsageInfoCollector.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
RegUsageInfoPropagate.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
RegisterBank.cpp [nfc][codegen] Move RegisterBank[Info].h under CodeGen 2022-03-01 21:53:25 -08:00
RegisterBankInfo.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
RegisterClassInfo.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
RegisterCoalescer.cpp [CodeGen] Use range-based for loops (NFC) 2021-12-06 08:49:10 -08:00
RegisterCoalescer.h
RegisterPressure.cpp
RegisterScavenging.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
RegisterUsageInfo.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
RemoveRedundantDebugValues.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
RenameIndependentSubregs.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
ReplaceWithVeclib.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
ResetMachineFunctionPass.cpp
SafeStack.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
SafeStackLayout.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
SafeStackLayout.h [SafeStack] Use Align instead of uint64_t 2021-12-15 14:40:56 -08:00
ScheduleDAG.cpp [llvm] Use llvm::reverse (NFC) 2021-12-12 16:13:49 -08:00
ScheduleDAGInstrs.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
ScheduleDAGPrinter.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
ScoreboardHazardRecognizer.cpp [llvm] Remove redundant member initialization (NFC) 2022-01-07 17:45:09 -08:00
ShadowStackGCLowering.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
ShrinkWrap.cpp [ShrinkWrap] check for PPC's non-callee-saved LR 2022-01-11 10:01:34 -08:00
SjLjEHPrepare.cpp
SlotIndexes.cpp [CodeGen] Use default member initialization (NFC) 2022-01-30 12:32:51 -08:00
SpillPlacement.cpp
SpillPlacement.h
SplitKit.cpp Simplify mask creation with llvm::seq. NFCI. 2022-02-05 23:35:41 +01:00
SplitKit.h Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
StackColoring.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
StackMapLivenessAnalysis.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
StackMaps.cpp
StackProtector.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
StackSlotColoring.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
SwiftErrorValueTracking.cpp
SwitchLoweringUtils.cpp [APInt] Normalize naming on keep constructors / predicate methods. 2021-09-09 09:50:24 -07:00
TailDuplication.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
TailDuplicator.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
TargetFrameLoweringImpl.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
TargetInstrInfo.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
TargetLoweringBase.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
TargetLoweringObjectFileImpl.cpp Revert rG9c542a5a4e1ba36c24e48185712779df52b7f7a6 "Lower `@llvm.global_dtors` using `__cxa_atexit` on MachO" 2022-03-15 13:01:35 +00:00
TargetOptionsImpl.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
TargetPassConfig.cpp Revert rG9c542a5a4e1ba36c24e48185712779df52b7f7a6 "Lower `@llvm.global_dtors` using `__cxa_atexit` on MachO" 2022-03-15 13:01:35 +00:00
TargetRegisterInfo.cpp Reduce dependencies on llvm/BinaryFormat/Dwarf.h 2022-02-04 11:44:03 +01:00
TargetSchedule.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
TargetSubtargetInfo.cpp [regalloc] Remove -consider-local-interval-cost 2022-03-14 10:49:16 -07:00
TwoAddressInstructionPass.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
TypePromotion.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
UnreachableBlockElim.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
VLIWMachineScheduler.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
ValueTypes.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
VirtRegMap.cpp [CodeGen] Use MachineInstr::operands (NFC) 2021-11-11 07:10:30 -08:00
WasmEHPrepare.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
WinEHPrepare.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
XRayInstrumentation.cpp Reapply [xray] add support for hexagon 2021-12-10 05:32:28 -08:00

README.txt

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %noreg, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side
effects).  Once this is in place, it would be even better to have tblgen
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStacks analysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.