forked from OSchip/llvm-project
135 lines
4.1 KiB
C++
135 lines
4.1 KiB
C++
//===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the Hexagon specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonSubtarget.h"
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#include "Hexagon.h"
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#include "HexagonRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <map>
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using namespace llvm;
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#define DEBUG_TYPE "hexagon-subtarget"
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#define GET_SUBTARGETINFO_CTOR
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#define GET_SUBTARGETINFO_TARGET_DESC
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#include "HexagonGenSubtargetInfo.inc"
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static cl::opt<bool> EnableMemOps("enable-hexagon-memops",
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cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(true),
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cl::desc("Generate V4 MEMOP in code generation for Hexagon target"));
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static cl::opt<bool> DisableMemOps("disable-hexagon-memops",
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cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(false),
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cl::desc("Do not generate V4 MEMOP in code generation for Hexagon target"));
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static cl::opt<bool> EnableIEEERndNear("enable-hexagon-ieee-rnd-near",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Generate non-chopped conversion from fp to int."));
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static cl::opt<bool> EnableBSBSched("enable-bsb-sched",
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cl::Hidden, cl::ZeroOrMore, cl::init(true));
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static cl::opt<bool> EnableHexagonHVXDouble("enable-hexagon-hvx-double",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Enable Hexagon Double Vector eXtensions"));
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static cl::opt<bool> EnableHexagonHVX("enable-hexagon-hvx",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Enable Hexagon Vector eXtensions"));
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static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Hexagon MI Scheduling"));
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static cl::opt<bool> EnableSubregLiveness("hexagon-subreg-liveness",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Enable subregister liveness tracking for Hexagon"));
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void HexagonSubtarget::initializeEnvironment() {
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UseMemOps = false;
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ModeIEEERndNear = false;
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UseBSBScheduling = false;
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}
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HexagonSubtarget &
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HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
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CPUString = HEXAGON_MC::selectHexagonCPU(getTargetTriple(), CPU);
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static std::map<StringRef, HexagonArchEnum> CpuTable {
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{ "hexagonv4", V4 },
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{ "hexagonv5", V5 },
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{ "hexagonv55", V55 },
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{ "hexagonv60", V60 },
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};
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auto foundIt = CpuTable.find(CPUString);
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if (foundIt != CpuTable.end())
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HexagonArchVersion = foundIt->second;
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else
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llvm_unreachable("Unrecognized Hexagon processor version");
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UseHVXOps = false;
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UseHVXDblOps = false;
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ParseSubtargetFeatures(CPUString, FS);
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if (EnableHexagonHVX.getPosition())
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UseHVXOps = EnableHexagonHVX;
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if (EnableHexagonHVXDouble.getPosition())
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UseHVXDblOps = EnableHexagonHVXDouble;
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return *this;
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}
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HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
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StringRef FS, const TargetMachine &TM)
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: HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU),
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InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
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FrameLowering() {
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initializeEnvironment();
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUString);
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// UseMemOps on by default unless disabled explicitly
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if (DisableMemOps)
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UseMemOps = false;
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else if (EnableMemOps)
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UseMemOps = true;
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else
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UseMemOps = false;
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if (EnableIEEERndNear)
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ModeIEEERndNear = true;
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else
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ModeIEEERndNear = false;
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UseBSBScheduling = hasV60TOps() && EnableBSBSched;
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}
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// Pin the vtable to this file.
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void HexagonSubtarget::anchor() {}
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bool HexagonSubtarget::enableMachineScheduler() const {
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if (DisableHexagonMISched.getNumOccurrences())
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return !DisableHexagonMISched;
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return true;
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}
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bool HexagonSubtarget::enableSubRegLiveness() const {
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return EnableSubregLiveness;
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}
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