llvm-project/llvm/test/CodeGen
Li Jia He bcae407a3c [PowerPC] Fix a conversion is not considered when the ISD::BR_CC node making the instruction selection
Summary:
 A signed comparison of i1 values produces the opposite result to an unsigned one if the condition code 
 includes less-than or greater-than. This is so because 1 is the most negative signed i1 number and the 
 most positive unsigned i1 number. The CR-logical operations used for such comparisons are non-commutative
 so for signed comparisons vs. unsigned ones, the input operands just need to be swapped.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D54825

llvm-svn: 347831
2018-11-29 03:04:39 +00:00
..
AArch64 [MachineScheduler] Add support for clustering mem ops with FI base operands 2018-11-28 12:00:28 +00:00
AMDGPU [AMDGPU] Disable DAG combine at -O0 2018-11-27 15:13:37 +00:00
ARC
ARM [LegalizeVectorTypes][X86][ARM][AArch64][PowerPC] Don't use SplitVecOp_TruncateHelper for FP_TO_SINT/UINT. 2018-11-26 21:12:39 +00:00
AVR [AVR] Reorder the CHECK lines in directmem.ll to match current trunk 2018-11-09 23:17:59 +00:00
BPF
Generic Moved dag-combine-select-undef.ll into amdgpu. NFC. 2018-11-17 00:17:15 +00:00
Hexagon [Hexagon] make test immune to improvements in undef simplification 2018-11-19 15:34:09 +00:00
Inputs
Lanai
MIR Revert r347490 as it breaks address sanitizer builds 2018-11-23 17:13:06 +00:00
MSP430 [MSP430] Optimize srl/sra in case of A >> (8 + N) 2018-11-19 10:43:02 +00:00
Mips [TargetLowering] expandFP_TO_UINT - improve fp16 support 2018-11-19 19:16:13 +00:00
NVPTX [LegalizeVectorTypes] Don't use SplitVecOp_TruncateHelper if we're heading towards scalarizing the type. 2018-11-23 02:32:13 +00:00
Nios2
PowerPC [PowerPC] Fix a conversion is not considered when the ISD::BR_CC node making the instruction selection 2018-11-29 03:04:39 +00:00
RISCV [RISCV] Constant materialisation for RV64I 2018-11-16 10:14:16 +00:00
SPARC Relax fast register allocator related test cases; NFC 2018-10-29 20:10:42 +00:00
SystemZ [SystemZ] make test immune to improvements in undef simplification 2018-11-18 16:50:44 +00:00
Thumb [SelectionDAG] swap select_cc operands to enable folding 2018-11-09 11:09:40 +00:00
Thumb2 [ARM] Enable spilling of the hGPR register class in Thumb2 2018-11-08 13:02:10 +00:00
WebAssembly [WebAssembly] WebAssemblyLowerEmscriptenEHSjLj: use getter/setter for accessing tempRet0 2018-11-20 19:25:07 +00:00
WinCFGuard
WinEH
X86 [x86] try select simplification for target-specific nodes 2018-11-28 22:51:04 +00:00
XCore Relax fast register allocator related test cases; NFC 2018-10-29 20:10:42 +00:00