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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel
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Matt Arsenault 7b9ed89dcf AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|EXTRACT}_VECTOR_ELT 
llvm-svn: 327269
 		2018-03-12 13:35:53 +00:00
..
amdgpu-irtranslator.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
inst-select-load-flat.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
inst-select-load-smrd.mir [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
inst-select-store-flat.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
irtranslator-amdgpu_vs.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
legalize-add.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
legalize-and.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
legalize-bitcast.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
legalize-constant.mir AMDGPU/GlobalISel: Make f64 constants legal 2018-02-26 17:20:43 +00:00
legalize-extract-vector-elt.mir AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|EXTRACT}_VECTOR_ELT 2018-03-12 13:35:53 +00:00
legalize-extract.mir AMDGPU/GlobalISel: Make some G_EXTRACTs legal 2018-03-05 16:25:15 +00:00
legalize-fadd.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
legalize-fcmp.mir AMDGPU/GlobalISel: Mark 32/64-bit G_FCMP as legal 2018-03-01 19:09:16 +00:00
legalize-fmul.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
legalize-fptosi.mir AMDGPU/GlobalISel: Mark 32-bit G_FPTOSI as legal 2018-03-01 19:04:25 +00:00
legalize-fptoui.mir AMDGPU/GlobalISel: Mark 32-bit G_FPTOUI as legal 2018-02-07 04:47:59 +00:00
legalize-icmp.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
legalize-insert-vector-elt.mir AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|EXTRACT}_VECTOR_ELT 2018-03-12 13:35:53 +00:00
legalize-merge-values.mir AMDGPU/GlobalISel: InstrMapping for G_MERGE_VALUES 2018-03-12 13:35:49 +00:00
legalize-mul.mir AMDGPU/GlobalISel: Make i32 mul legal 2018-03-01 19:22:05 +00:00
legalize-or.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
legalize-select.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
legalize-shl.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
legalize-unmerge-values.mir AMDGPU/GlobalISel: Make some G_MERGE_VALUEs legal 2018-03-12 13:35:43 +00:00
legalize-xor.mir AMDGPU/GlobalISel: Make i32 xor legal 2018-03-01 19:09:21 +00:00
legalize-zext.mir AMDGPU/GlobalISel: Mark i32->i64 zext as legal 2018-03-01 20:56:21 +00:00
lit.local.cfg AMDGPU: Add lit.local.cfg to disable global-isel tests when global-isel is disabled 2017-05-12 17:59:30 +00:00
regbankselect-amdgcn-exp-compr.mir AMDGPU/GlobalISel: InstrMapping for llvm.amdgcn.exp.compr 2018-03-01 20:40:55 +00:00
regbankselect-amdgcn-exp.mir AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.exp 2018-03-01 20:24:37 +00:00
regbankselect-amdgcn.cvt.pkrtz.mir AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.cvt.pkrtz 2018-03-01 21:25:30 +00:00
regbankselect-and.mir AMDGPU/GlobalISel: Define instruction mapping for G_AND 2018-03-02 01:22:01 +00:00
regbankselect-bitcast.mir AMDGPU/GlobalISel: Define instruction mapping for G_BITCAST 2018-03-01 20:59:44 +00:00
regbankselect-default.mir AMDGPU/GlobalISel: Define instruction mapping for G_IMPLICIT_DEF 2018-03-01 19:16:52 +00:00
regbankselect-extract-vector-elt.mir AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|EXTRACT}_VECTOR_ELT 2018-03-12 13:35:53 +00:00
regbankselect-extract.mir AMDGPU/GlobalISel: Add InstrMapping for G_EXTRACT 2018-03-05 16:25:18 +00:00
regbankselect-fadd.mir AMDGPU/GlobalISel: Define instruction mapping for G_FADD 2018-03-02 01:22:13 +00:00
regbankselect-fcmp.mir AMDGPU/GlobalISel: Define InstrMappings for G_FCMP 2018-03-02 16:53:15 +00:00
regbankselect-fmul.mir AMDGPU/GlobalISel: Define instruction mapping for G_FMUL 2018-03-02 02:17:01 +00:00
regbankselect-fptosi.mir AMDGPU/GlobalISel: Define instruction mapping for G_FPTOSI 2018-03-02 02:19:16 +00:00
regbankselect-fptoui.mir AMDGPU/GlobalISel: Define instruction mapping for G_FPTOUI 2018-03-02 02:19:11 +00:00
regbankselect-icmp.mir AMDGPU/GlobalISel: Define InstrMappings for G_ICMP 2018-03-01 19:27:10 +00:00
regbankselect-insert-vector-elt.mir AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|EXTRACT}_VECTOR_ELT 2018-03-12 13:35:53 +00:00
regbankselect-maxnum.mir AMDGPU/GlobalISel: Define instruction mapping for @llvm.maxnum 2018-03-02 12:23:00 +00:00
regbankselect-merge-values.mir AMDGPU/GlobalISel: InstrMapping for G_MERGE_VALUES 2018-03-12 13:35:49 +00:00
regbankselect-minnum.mir AMDGPU/GlobalISel: Define instruction mapping for @llvm.minnum 2018-03-02 16:40:17 +00:00
regbankselect-or.mir AMDGPU/GlobalISel: Define instruction mapping for G_OR 2018-03-01 21:25:25 +00:00
regbankselect-shl.mir AMDGPU/GlobalISel: Define instruction mapping for G_SHL 2018-03-02 01:22:10 +00:00
regbankselect-trunc.mir AMDGPU/GlobalISel: InstrMapping for G_TRUNC 2018-03-02 16:55:33 +00:00
regbankselect-xor.mir AMDGPU/GlobalISel: Define instruction mapping for G_XOR 2018-03-02 01:22:06 +00:00
regbankselect-zext.mir AMDGPU/GlobalISel: InstrMapping for G_ZEXT 2018-03-02 16:55:37 +00:00
regbankselect.mir [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00
shader-epilogs.ll Re-commit AMDGPU/GlobalISel: Add support for simple shaders 2017-01-30 21:56:46 +00:00
smrd.ll [AMDGPU] Change constant addr space to 4 2018-02-13 18:00:25 +00:00