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llvm-project/llvm/lib/Target/AArch64
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Jessica Paquette 1cb18ec4ec [MachineOutliner] Outline both register save calls + no LR save calls together 
Instead of treating the outlined functions for these as distinct frames, they
should be combined into one case. Neither allows for stack fixups, and both
generate the same frame. Thus, they ought to be considered one case.

This makes the code far easier to understand, for one thing. It also offers
some small code size improvements. It's fairly rare to see a class of outlined
functions that doesn't fall entirely into one variant (on CTMark anyway). It
does happen from time to time though.

This mostly offers some serious simplification.

Also update the test to show the added functionality.

llvm-svn: 348036
 		2018-11-30 21:14:58 +00:00
..
AsmParser Revert r347490 as it breaks address sanitizer builds 2018-11-23 17:13:06 +00:00
Disassembler [AArch64][v8.5A] Add Memory Tagging instructions 2018-10-02 10:04:39 +00:00
InstPrinter [AArch64][v8.5A] Add Branch Target Identification instructions 2018-09-27 14:54:33 +00:00
MCTargetDesc [TableGen] Refactor macro names (NFC) 2018-11-27 20:58:27 +00:00
TargetInfo
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Utils [AArch64][v8.5A] Add Branch Target Identification instructions 2018-09-27 14:54:33 +00:00
AArch64.h AArch64: add a pass to compress jump-table entries when possible. 2018-10-24 20:19:09 +00:00
AArch64.td [AArch64] Refactor the scheduling predicates (1/3) (NFC) 2018-11-26 21:47:28 +00:00
AArch64A53Fix835769.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64A57FPLoadBalancing.cpp llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...) 2018-09-27 02:13:45 +00:00
AArch64AdvSIMDScalarPass.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64AsmPrinter.cpp [CodeGen] Support custom format of stack maps 2018-11-26 18:43:48 +00:00
AArch64BranchTargets.cpp [AArch64][v8.5A] Branch Target Identification code-generation pass 2018-10-08 14:04:24 +00:00
AArch64CallLowering.cpp [AArch64] Support adding X[8-15,18] registers as CSRs. 2018-09-22 22:17:50 +00:00
AArch64CallLowering.h [GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per Value 2018-08-02 08:33:31 +00:00
AArch64CallingConvention.h
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AArch64CallingConvention.td [ARM64] [Windows] Exception handling support in frame lowering 2018-10-31 09:27:01 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
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AArch64CollectLOH.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64CompressJumpTables.cpp AArch64: add a pass to compress jump-table entries when possible. 2018-10-24 20:19:09 +00:00
AArch64CondBrTuning.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64ConditionOptimizer.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64ConditionalCompares.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64DeadRegisterDefinitionsPass.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64ExpandPseudoInsts.cpp [AArch64] Add Tiny Code Model for AArch64 2018-08-22 11:31:39 +00:00
AArch64FalkorHWPFFix.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64FastISel.cpp [COFF, ARM64] Implement Intrinsic.sponentry for AArch64 2018-11-01 23:22:25 +00:00
AArch64FrameLowering.cpp AArch64: Don't emit CFI for SCS register in nounwind functions. 2018-11-30 21:04:25 +00:00
AArch64FrameLowering.h [ARM64] [Windows] Handle funclets 2018-11-09 23:33:30 +00:00
AArch64GenRegisterBankInfo.def
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AArch64ISelDAGToDAG.cpp [AArch64][v8.5A] Add speculation restriction system registers 2018-09-27 14:05:46 +00:00
AArch64ISelLowering.cpp [SelectionDAG][AArch64][X86] Move legalization of vector MULHS/MULHU from LegalizeDAG to LegalizeVectorOps 2018-11-29 19:36:17 +00:00
AArch64ISelLowering.h [ARM64] [Windows] Handle funclets 2018-11-09 23:33:30 +00:00
AArch64InstrAtomics.td
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AArch64InstrFormats.td [AArch64] Add support for UDF instruction 2018-10-30 11:06:50 +00:00
AArch64InstrInfo.cpp [MachineOutliner] Outline both register save calls + no LR save calls together 2018-11-30 21:14:58 +00:00
AArch64InstrInfo.h [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operand 2018-11-28 12:00:20 +00:00
AArch64InstrInfo.td [SelectionDAG][AArch64][X86] Move legalization of vector MULHS/MULHU from LegalizeDAG to LegalizeVectorOps 2018-11-29 19:36:17 +00:00
AArch64InstructionSelector.cpp [AArch64] Add Tiny Code Model for AArch64 2018-08-22 11:31:39 +00:00
AArch64LegalizerInfo.cpp [GlobalISel] Fix a bug in LegalizeRuleSet::clampMaxNumElements 2018-11-01 19:01:53 +00:00
AArch64LegalizerInfo.h
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AArch64LoadStoreOptimizer.cpp [MI] Change the array of `MachineMemOperand` pointers to be 2018-08-16 21:30:05 +00:00
AArch64MCInstLower.cpp [ARM64] [Windows] Handle funclets 2018-11-09 23:33:30 +00:00
AArch64MCInstLower.h
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AArch64MachineFunctionInfo.h [COFF, ARM64] Make sure to forward arguments from vararg to musttail vararg 2018-10-30 20:46:10 +00:00
AArch64MacroFusion.cpp [PATCH] [NFC][AArch64] Fix refactoring of macro fusion 2018-10-16 17:41:45 +00:00
AArch64MacroFusion.h
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AArch64PBQPRegAlloc.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64PBQPRegAlloc.h
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AArch64PerfectShuffle.h
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AArch64PfmCounters.td [llvm-exegesis][NFC] Add a way to declare the default counter binding for unbound CPUs for a target. 2018-11-09 13:15:32 +00:00
AArch64PreLegalizerCombiner.cpp Add the missing new files from r343654 2018-10-03 02:21:30 +00:00
AArch64PromoteConstant.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64RedundantCopyElimination.cpp [CodeGen][AArch64] Use RegUnits to track register aliases. (NFC) 2018-05-23 17:49:38 +00:00
AArch64RegisterBankInfo.cpp
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AArch64RegisterBankInfo.h
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AArch64RegisterBanks.td
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AArch64RegisterInfo.cpp [ARM64] [Windows] Handle funclets 2018-11-09 23:33:30 +00:00
AArch64RegisterInfo.h [ARM64] [Windows] Handle funclets 2018-11-09 23:33:30 +00:00
AArch64RegisterInfo.td [AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI 2018-10-08 14:09:15 +00:00
AArch64SIMDInstrOpt.cpp [TargetSchedule] shrink interface for init(); NFCI 2018-04-08 19:56:04 +00:00
AArch64SVEInstrInfo.td [AArch64][SVE] Asm: Enable instructions to be prefixed. 2018-07-30 16:05:45 +00:00
AArch64SchedA53.td [AArch64] Clean-up a few over-eager regexps in models. 2018-03-23 11:00:42 +00:00
AArch64SchedA57.td
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AArch64SchedA57WriteRes.td
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AArch64SchedCyclone.td
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AArch64SchedExynosM1.td [AArch64] Refactor Exynos machine model 2018-10-24 21:40:43 +00:00
AArch64SchedExynosM3.td [AArch64] Refactor Exynos machine model 2018-10-24 21:40:43 +00:00
AArch64SchedFalkor.td [TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. 2018-03-18 19:56:15 +00:00
AArch64SchedFalkorDetails.td [AArch64][Falkor] Correct load/store increment scheduling details 2018-03-20 13:46:35 +00:00
AArch64SchedKryo.td [TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. 2018-03-18 19:56:15 +00:00
AArch64SchedKryoDetails.td
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AArch64SchedPredicates.td [AArch64] Refactor the scheduling predicates (3/3) (NFC) 2018-11-26 21:47:46 +00:00
AArch64SchedThunderX.td [TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. 2018-03-18 19:56:15 +00:00
AArch64SchedThunderX2T99.td [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles. 2018-06-13 09:41:49 +00:00
AArch64Schedule.td [AArch64] Refactor the scheduling predicates (3/3) (NFC) 2018-11-26 21:47:46 +00:00
AArch64SelectionDAGInfo.cpp
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AArch64SelectionDAGInfo.h
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AArch64StorePairSuppress.cpp [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operand 2018-11-28 12:00:20 +00:00
AArch64Subtarget.cpp [AArch64] Refactor the scheduling predicates (1/3) (NFC) 2018-11-26 21:47:28 +00:00
AArch64Subtarget.h [AArch64] Support HiSilicon's TSV110 processor 2018-11-09 19:32:08 +00:00
AArch64SystemOperands.td [AArch64][v8.5A] Add Memory Tagging system registers 2018-10-02 09:54:35 +00:00
AArch64TargetMachine.cpp [GlobalISel] Make EnableGlobalISel always set when GISel is enabled 2018-11-29 12:56:32 +00:00
AArch64TargetMachine.h
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AArch64TargetObjectFile.cpp [AArch64] DWARF: do not generate AT_location for thread local 2018-08-01 23:46:49 +00:00
AArch64TargetObjectFile.h Move TargetLoweringObjectFile from CodeGen to Target to fix layering 2018-03-23 23:58:19 +00:00
AArch64TargetTransformInfo.cpp [LV] Support vectorization of interleave-groups that require an epilog under 2018-10-31 09:57:56 +00:00
AArch64TargetTransformInfo.h [LV] Support vectorization of interleave-groups that require an epilog under 2018-10-31 09:57:56 +00:00
CMakeLists.txt [llvm-exegesis][NFC] Add a way to declare the default counter binding for unbound CPUs for a target. 2018-11-09 13:15:32 +00:00
LLVMBuild.txt
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SVEInstrFormats.td Remove extra whitespace. NFC. (test commit) 2018-09-28 08:45:28 +00:00