forked from OSchip/llvm-project
65 lines
2.0 KiB
TableGen
65 lines
2.0 KiB
TableGen
//===-- VIInstructions.td - VI Instruction Defintions ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Instruction definitions for VI and newer.
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//===----------------------------------------------------------------------===//
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let SubtargetPredicate = isVI in {
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defm BUFFER_LOAD_DWORD_VI : MUBUF_Load_Helper_vi <
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0x14, "buffer_load_dword", VGPR_32, i32, global_load
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>;
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defm BUFFER_LOAD_FORMAT_XYZW_VI : MUBUF_Load_Helper_vi <
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0x03, "buffer_load_format_xyzw", VReg_128
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>;
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} // End SubtargetPredicate = isVI
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//===----------------------------------------------------------------------===//
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// SMEM Patterns
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//===----------------------------------------------------------------------===//
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let Predicates = [isVI] in {
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// 1. Offset as 8bit DWORD immediate
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def : Pat <
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(SIload_constant v4i32:$sbase, IMM20bit:$offset),
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(S_BUFFER_LOAD_DWORD_IMM $sbase, (as_i32imm $offset))
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>;
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//===----------------------------------------------------------------------===//
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// MUBUF Patterns
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//===----------------------------------------------------------------------===//
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// Offset in an 32Bit VGPR
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def : Pat <
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(SIload_constant v4i32:$sbase, i32:$voff),
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(BUFFER_LOAD_DWORD_VI_OFFEN $sbase, $voff, 0, 0, 0, 0, 0)
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>;
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// Offset in an 32Bit VGPR
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def : Pat <
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(SIload_constant v4i32:$sbase, i32:$voff),
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(BUFFER_LOAD_DWORD_VI_OFFEN $sbase, $voff, 0, 0, 0, 0, 0)
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>;
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/* int_SI_vs_load_input */
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def : Pat<
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(SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
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(BUFFER_LOAD_FORMAT_XYZW_VI_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
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>;
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defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_VI_OFFSET,
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BUFFER_LOAD_DWORD_VI_OFFEN,
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BUFFER_LOAD_DWORD_VI_IDXEN,
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BUFFER_LOAD_DWORD_VI_BOTHEN>;
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} // End Predicates = [isVI]
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