llvm-project/llvm/test/CodeGen/MIR
Quentin Colombet 876ddf8107 [MIR] Teach the parser how to deal with register banks.
llvm-svn: 265802
2016-04-08 16:40:43 +00:00
..
AArch64 [AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth() 2016-03-31 20:53:47 +00:00
AMDGPU When printing MIR, output to errs() rather than outs(). 2016-02-19 00:18:46 +00:00
ARM Add MachineFunctionProperty checks for AllVRegsAllocated for target passes 2016-04-04 17:09:25 +00:00
Generic When printing MIR, output to errs() rather than outs(). 2016-02-19 00:18:46 +00:00
Mips When printing MIR, output to errs() rather than outs(). 2016-02-19 00:18:46 +00:00
NVPTX When printing MIR, output to errs() rather than outs(). 2016-02-19 00:18:46 +00:00
PowerPC When printing MIR, output to errs() rather than outs(). 2016-02-19 00:18:46 +00:00
X86 [MIR] Teach the parser how to deal with register banks. 2016-04-08 16:40:43 +00:00