forked from OSchip/llvm-project
161 lines
4.2 KiB
LLVM
161 lines
4.2 KiB
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-bit=0 < %s | FileCheck %s
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; Optimized bitwise operations.
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define i32 @my_clrbit(i32 %x) nounwind {
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entry:
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; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
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%x.addr = alloca i32, align 4
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store i32 %x, i32* %x.addr, align 4
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%0 = load i32, i32* %x.addr, align 4
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%and = and i32 %0, 2147483647
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ret i32 %and
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}
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define i64 @my_clrbit2(i64 %x) nounwind {
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entry:
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; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
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%x.addr = alloca i64, align 8
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store i64 %x, i64* %x.addr, align 8
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%0 = load i64, i64* %x.addr, align 8
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%and = and i64 %0, -2147483649
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ret i64 %and
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}
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define i64 @my_clrbit3(i64 %x) nounwind {
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entry:
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; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
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%x.addr = alloca i64, align 8
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store i64 %x, i64* %x.addr, align 8
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%0 = load i64, i64* %x.addr, align 8
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%and = and i64 %0, 9223372036854775807
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ret i64 %and
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}
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define i32 @my_clrbit4(i32 %x) nounwind {
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entry:
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; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13)
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%x.addr = alloca i32, align 4
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store i32 %x, i32* %x.addr, align 4
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%0 = load i32, i32* %x.addr, align 4
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%and = and i32 %0, -8193
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ret i32 %and
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}
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define i64 @my_clrbit5(i64 %x) nounwind {
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entry:
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; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13)
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%x.addr = alloca i64, align 8
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store i64 %x, i64* %x.addr, align 8
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%0 = load i64, i64* %x.addr, align 8
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%and = and i64 %0, -8193
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ret i64 %and
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}
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define i64 @my_clrbit6(i64 %x) nounwind {
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entry:
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; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #27)
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%x.addr = alloca i64, align 8
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store i64 %x, i64* %x.addr, align 8
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%0 = load i64, i64* %x.addr, align 8
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%and = and i64 %0, -576460752303423489
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ret i64 %and
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}
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define zeroext i16 @my_setbit(i16 zeroext %crc) nounwind {
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entry:
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; CHECK: memh(r{{[0-9]+}}+#0){{ *}}={{ *}}setbit(#15)
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%crc.addr = alloca i16, align 2
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store i16 %crc, i16* %crc.addr, align 2
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%0 = load i16, i16* %crc.addr, align 2
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%conv = zext i16 %0 to i32
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%or = or i32 %conv, 32768
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%conv1 = trunc i32 %or to i16
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store i16 %conv1, i16* %crc.addr, align 2
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%1 = load i16, i16* %crc.addr, align 2
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ret i16 %1
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}
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define i32 @my_setbit2(i32 %x) nounwind {
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entry:
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15)
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%x.addr = alloca i32, align 4
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store i32 %x, i32* %x.addr, align 4
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%0 = load i32, i32* %x.addr, align 4
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%or = or i32 %0, 32768
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ret i32 %or
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}
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define i64 @my_setbit3(i64 %x) nounwind {
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entry:
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15)
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%x.addr = alloca i64, align 8
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store i64 %x, i64* %x.addr, align 8
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%0 = load i64, i64* %x.addr, align 8
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%or = or i64 %0, 32768
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ret i64 %or
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}
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define i32 @my_setbit4(i32 %x) nounwind {
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entry:
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #31)
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%x.addr = alloca i32, align 4
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store i32 %x, i32* %x.addr, align 4
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%0 = load i32, i32* %x.addr, align 4
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%or = or i32 %0, -2147483648
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ret i32 %or
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}
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define i64 @my_setbit5(i64 %x) nounwind {
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entry:
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #13)
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%x.addr = alloca i64, align 8
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store i64 %x, i64* %x.addr, align 8
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%0 = load i64, i64* %x.addr, align 8
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%or = or i64 %0, 35184372088832
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ret i64 %or
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}
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define zeroext i16 @my_togglebit(i16 zeroext %crc) nounwind {
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entry:
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; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15)
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%crc.addr = alloca i16, align 2
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store i16 %crc, i16* %crc.addr, align 2
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%0 = load i16, i16* %crc.addr, align 2
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%conv = zext i16 %0 to i32
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%xor = xor i32 %conv, 32768
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%conv1 = trunc i32 %xor to i16
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store i16 %conv1, i16* %crc.addr, align 2
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%1 = load i16, i16* %crc.addr, align 2
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ret i16 %1
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}
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define i32 @my_togglebit2(i32 %x) nounwind {
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entry:
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; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15)
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%x.addr = alloca i32, align 4
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store i32 %x, i32* %x.addr, align 4
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%0 = load i32, i32* %x.addr, align 4
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%xor = xor i32 %0, 32768
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ret i32 %xor
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}
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define i64 @my_togglebit3(i64 %x) nounwind {
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entry:
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; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15)
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%x.addr = alloca i64, align 8
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store i64 %x, i64* %x.addr, align 8
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%0 = load i64, i64* %x.addr, align 8
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%xor = xor i64 %0, 32768
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ret i64 %xor
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}
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define i64 @my_togglebit4(i64 %x) nounwind {
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entry:
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; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #20)
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%x.addr = alloca i64, align 8
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store i64 %x, i64* %x.addr, align 8
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%0 = load i64, i64* %x.addr, align 8
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%xor = xor i64 %0, 4503599627370496
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ret i64 %xor
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}
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