forked from OSchip/llvm-project
33 lines
1.3 KiB
TableGen
33 lines
1.3 KiB
TableGen
//===--- HexagonIICScalar.td ----------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// These itinerary class descriptions are based on the instruction timing
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// classes as per V62. Curretnly, they are just extracted from
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// HexagonScheduleV62.td but will soon be auto-generated by HexagonGen.py.
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class PseudoItin {
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list<InstrItinData> PseudoItin_list = [
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InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
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[1, 1, 1]>,
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InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
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InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
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InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
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];
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}
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class ScalarItin {
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list<InstrItinData> ScalarItin_list = [
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InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
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[3, 1], [Hex_FWD, Hex_FWD]>,
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InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
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[1, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>
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];
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}
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