forked from OSchip/llvm-project
243 lines
6.2 KiB
LLVM
243 lines
6.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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declare i32 @llvm.ctpop.i32(i32)
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declare i32 @llvm.ctlz.i32(i32, i1)
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declare i32 @llvm.cttz.i32(i32, i1)
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define i64 @test1(i32 %x) {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.ctpop.i32(i32 %x)
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; CHECK-NEXT: [[S1:%.*]] = zext i32 [[T]] to i64
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; CHECK-NEXT: ret i64 [[S1]]
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;
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%t = call i32 @llvm.ctpop.i32(i32 %x)
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%s = sext i32 %t to i64
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ret i64 %s
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}
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define i64 @test2(i32 %x) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
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; CHECK-NEXT: [[S1:%.*]] = zext i32 [[T]] to i64
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; CHECK-NEXT: ret i64 [[S1]]
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;
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%t = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
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%s = sext i32 %t to i64
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ret i64 %s
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}
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define i64 @test3(i32 %x) {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.cttz.i32(i32 %x, i1 true)
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; CHECK-NEXT: [[S1:%.*]] = zext i32 [[T]] to i64
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; CHECK-NEXT: ret i64 [[S1]]
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;
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%t = call i32 @llvm.cttz.i32(i32 %x, i1 true)
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%s = sext i32 %t to i64
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ret i64 %s
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}
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define i64 @test4(i32 %x) {
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; CHECK-LABEL: @test4(
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; CHECK-NEXT: [[T:%.*]] = udiv i32 %x, 3
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; CHECK-NEXT: [[S1:%.*]] = zext i32 [[T]] to i64
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; CHECK-NEXT: ret i64 [[S1]]
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;
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%t = udiv i32 %x, 3
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%s = sext i32 %t to i64
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ret i64 %s
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}
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define i64 @test5(i32 %x) {
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; CHECK-LABEL: @test5(
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; CHECK-NEXT: [[T:%.*]] = urem i32 %x, 30000
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; CHECK-NEXT: [[S1:%.*]] = zext i32 [[T]] to i64
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; CHECK-NEXT: ret i64 [[S1]]
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;
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%t = urem i32 %x, 30000
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%s = sext i32 %t to i64
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ret i64 %s
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}
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define i64 @test6(i32 %x) {
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; CHECK-LABEL: @test6(
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; CHECK-NEXT: [[U:%.*]] = lshr i32 %x, 3
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; CHECK-NEXT: [[T:%.*]] = mul nuw nsw i32 [[U]], 3
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; CHECK-NEXT: [[S1:%.*]] = zext i32 [[T]] to i64
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; CHECK-NEXT: ret i64 [[S1]]
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;
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%u = lshr i32 %x, 3
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%t = mul i32 %u, 3
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%s = sext i32 %t to i64
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ret i64 %s
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}
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define i64 @test7(i32 %x) {
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; CHECK-LABEL: @test7(
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; CHECK-NEXT: [[T:%.*]] = and i32 %x, 511
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; CHECK-NEXT: [[U:%.*]] = sub nsw i32 20000, [[T]]
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; CHECK-NEXT: [[S1:%.*]] = zext i32 [[U]] to i64
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; CHECK-NEXT: ret i64 [[S1]]
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;
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%t = and i32 %x, 511
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%u = sub i32 20000, %t
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%s = sext i32 %u to i64
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ret i64 %s
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}
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define i32 @test8(i8 %a, i32 %f, i1 %p, i32* %z) {
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; CHECK-LABEL: @test8(
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; CHECK-NEXT: [[D:%.*]] = lshr i32 %f, 24
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; CHECK-NEXT: [[N:%.*]] = select i1 %p, i32 [[D]], i32 0
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; CHECK-NEXT: ret i32 [[N]]
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;
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%d = lshr i32 %f, 24
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%e = select i1 %p, i32 %d, i32 0
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%s = trunc i32 %e to i16
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%n = sext i16 %s to i32
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ret i32 %n
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}
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; rdar://6013816
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define i16 @test9(i16 %t, i1 %cond) {
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; CHECK-LABEL: @test9(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 %cond, label %T, label %F
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; CHECK: T:
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; CHECK-NEXT: br label %F
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; CHECK: F:
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; CHECK-NEXT: [[V_OFF0:%.*]] = phi i16 [ %t, %T ], [ 42, %entry ]
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; CHECK-NEXT: ret i16 [[V_OFF0]]
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;
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entry:
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br i1 %cond, label %T, label %F
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T:
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%t2 = sext i16 %t to i32
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br label %F
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F:
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%V = phi i32 [%t2, %T], [42, %entry]
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%W = trunc i32 %V to i16
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ret i16 %W
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}
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; PR2638
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define i32 @test10(i32 %i) {
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; CHECK-LABEL: @test10(
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; CHECK-NEXT: [[B1:%.*]] = shl i32 %i, 30
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; CHECK-NEXT: [[B:%.*]] = ashr exact i32 [[B1]], 30
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; CHECK-NEXT: ret i32 [[B]]
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;
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%tmp12 = trunc i32 %i to i8
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%tmp16 = shl i8 %tmp12, 6
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%a = ashr i8 %tmp16, 6
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%b = sext i8 %a to i32
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ret i32 %b
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}
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define void @test11(<2 x i16> %srcA, <2 x i16> %srcB, <2 x i16>* %dst) {
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; CHECK-LABEL: @test11(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i16> %srcB, %srcA
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; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> [[CMP]] to <2 x i16>
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; CHECK-NEXT: store <2 x i16> [[SEXT]], <2 x i16>* %dst, align 4
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; CHECK-NEXT: ret void
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;
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%cmp = icmp eq <2 x i16> %srcB, %srcA
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%sext = sext <2 x i1> %cmp to <2 x i16>
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%tmask = ashr <2 x i16> %sext, <i16 15, i16 15>
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store <2 x i16> %tmask, <2 x i16>* %dst
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ret void
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}
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define i64 @test12(i32 %x) {
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; CHECK-LABEL: @test12(
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; CHECK-NEXT: [[SHR:%.*]] = lshr i32 %x, 1
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[SHR]]
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; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[SUB]] to i64
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; CHECK-NEXT: ret i64 [[CONV]]
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;
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%shr = lshr i32 %x, 1
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%sub = sub nsw i32 0, %shr
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%conv = sext i32 %sub to i64
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ret i64 %conv
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}
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define i32 @test13(i32 %x) {
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; CHECK-LABEL: @test13(
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; CHECK-NEXT: [[AND:%.*]] = lshr i32 %x, 3
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 1
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; CHECK-NEXT: [[SEXT:%.*]] = add nsw i32 [[TMP1]], -1
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; CHECK-NEXT: ret i32 [[SEXT]]
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;
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%and = and i32 %x, 8
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%cmp = icmp eq i32 %and, 0
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%ext = sext i1 %cmp to i32
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ret i32 %ext
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}
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define i32 @test14(i16 %x) {
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; CHECK-LABEL: @test14(
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; CHECK-NEXT: [[AND:%.*]] = lshr i16 %x, 4
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; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[AND]], 1
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; CHECK-NEXT: [[SEXT:%.*]] = add nsw i16 [[TMP1]], -1
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; CHECK-NEXT: [[EXT:%.*]] = sext i16 [[SEXT]] to i32
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; CHECK-NEXT: ret i32 [[EXT]]
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;
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%and = and i16 %x, 16
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%cmp = icmp ne i16 %and, 16
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%ext = sext i1 %cmp to i32
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ret i32 %ext
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}
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define i32 @test15(i32 %x) {
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; CHECK-LABEL: @test15(
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; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 27
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; CHECK-NEXT: [[SEXT:%.*]] = ashr i32 [[TMP1]], 31
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; CHECK-NEXT: ret i32 [[SEXT]]
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;
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%and = and i32 %x, 16
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%cmp = icmp ne i32 %and, 0
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%ext = sext i1 %cmp to i32
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ret i32 %ext
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}
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define i32 @test16(i16 %x) {
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; CHECK-LABEL: @test16(
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; CHECK-NEXT: [[TMP1:%.*]] = shl i16 %x, 12
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; CHECK-NEXT: [[SEXT:%.*]] = ashr i16 [[TMP1]], 15
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; CHECK-NEXT: [[EXT:%.*]] = sext i16 [[SEXT]] to i32
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; CHECK-NEXT: ret i32 [[EXT]]
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;
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%and = and i16 %x, 8
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%cmp = icmp eq i16 %and, 8
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%ext = sext i1 %cmp to i32
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ret i32 %ext
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}
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define i32 @test17(i1 %x) {
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; CHECK-LABEL: @test17(
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; CHECK-NEXT: [[C2:%.*]] = zext i1 %x to i32
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; CHECK-NEXT: ret i32 [[C2]]
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;
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%c1 = sext i1 %x to i32
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%c2 = sub i32 0, %c1
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ret i32 %c2
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}
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define i32 @test18(i16 %x) {
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; CHECK-LABEL: @test18(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i16 %x, 0
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[TMP1]], i16 %x, i16 0
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; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[SEL]] to i32
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; CHECK-NEXT: ret i32 [[TMP2]]
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;
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%cmp = icmp slt i16 %x, 0
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%sel = select i1 %cmp, i16 0, i16 %x
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%ext = sext i16 %sel to i32
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ret i32 %ext
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}
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