forked from OSchip/llvm-project
259 lines
9.5 KiB
C++
259 lines
9.5 KiB
C++
//===-- TestPPC64InstEmulation.cpp ----------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "gtest/gtest.h"
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#include <vector>
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#include "Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.h"
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#include "lldb/Core/Address.h"
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#include "lldb/Core/AddressRange.h"
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#include "lldb/Symbol/UnwindPlan.h"
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#include "lldb/Target/UnwindAssembly.h"
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#include "lldb/Utility/ArchSpec.h"
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#include "Plugins/Disassembler/LLVMC/DisassemblerLLVMC.h"
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#include "Plugins/Instruction/PPC64/EmulateInstructionPPC64.h"
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#include "Plugins/Process/Utility/lldb-ppc64le-register-enums.h"
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#include "llvm/Support/TargetSelect.h"
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using namespace lldb;
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using namespace lldb_private;
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class TestPPC64InstEmulation : public testing::Test {
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public:
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static void SetUpTestCase();
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static void TearDownTestCase();
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// virtual void SetUp() override { }
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// virtual void TearDown() override { }
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protected:
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};
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void TestPPC64InstEmulation::SetUpTestCase() {
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llvm::InitializeAllTargets();
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llvm::InitializeAllAsmPrinters();
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llvm::InitializeAllTargetMCs();
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llvm::InitializeAllDisassemblers();
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DisassemblerLLVMC::Initialize();
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EmulateInstructionPPC64::Initialize();
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}
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void TestPPC64InstEmulation::TearDownTestCase() {
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DisassemblerLLVMC::Terminate();
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EmulateInstructionPPC64::Terminate();
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}
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TEST_F(TestPPC64InstEmulation, TestSimpleFunction) {
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ArchSpec arch("powerpc64le-linux-gnu");
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std::unique_ptr<UnwindAssemblyInstEmulation> engine(
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static_cast<UnwindAssemblyInstEmulation *>(
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UnwindAssemblyInstEmulation::CreateInstance(arch)));
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ASSERT_NE(nullptr, engine);
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UnwindPlan::RowSP row_sp;
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AddressRange sample_range;
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UnwindPlan unwind_plan(eRegisterKindLLDB);
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UnwindPlan::Row::RegisterLocation regloc;
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// prologue and epilogue of:
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// int main() {
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// int i = test();
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// return i;
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// }
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//
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// compiled with clang -O0 -g
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uint8_t data[] = {
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// prologue
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0x02, 0x10, 0x40, 0x3c, // 0: lis r2, 4098
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0x00, 0x7f, 0x42, 0x38, // 4: addi r2, r2, 32512
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0xa6, 0x02, 0x08, 0x7c, // 8: mflr r0
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0xf8, 0xff, 0xe1, 0xfb, // 12: std r31, -8(r1)
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0x10, 0x00, 0x01, 0xf8, // 16: std r0, 16(r1)
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0x91, 0xff, 0x21, 0xf8, // 20: stdu r1, -112(r1)
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0x78, 0x0b, 0x3f, 0x7c, // 24: mr r31, r1
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0x00, 0x00, 0x60, 0x38, // 28: li r3, 0
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0x64, 0x00, 0x7f, 0x90, // 32: stw r3, 100(r31)
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// epilogue
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0x70, 0x00, 0x21, 0x38, // 36: addi r1, r1, 112
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0x10, 0x00, 0x01, 0xe8, // 40: ld r0, 16(r1)
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0xf8, 0xff, 0xe1, 0xeb, // 44: ld r31, -8(r1)
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0xa6, 0x03, 0x08, 0x7c, // 48: mtlr r0
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0x20, 0x00, 0x80, 0x4e // 52: blr
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};
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sample_range = AddressRange(0x1000, sizeof(data));
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EXPECT_TRUE(engine->GetNonCallSiteUnwindPlanFromAssembly(
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sample_range, data, sizeof(data), unwind_plan));
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// 0: CFA=sp+0
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row_sp = unwind_plan.GetRowForFunctionOffset(0);
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EXPECT_EQ(0ull, row_sp->GetOffset());
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EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_r1_ppc64le);
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EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
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EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
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// 1: CFA=sp+0 => fp=[CFA-8]
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row_sp = unwind_plan.GetRowForFunctionOffset(16);
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EXPECT_EQ(16ull, row_sp->GetOffset());
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EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_r1_ppc64le);
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EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
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EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
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EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_r31_ppc64le, regloc));
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EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
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EXPECT_EQ(-8, regloc.GetOffset());
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// 2: CFA=sp+0 => fp=[CFA-8] lr=[CFA+16]
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row_sp = unwind_plan.GetRowForFunctionOffset(20);
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EXPECT_EQ(20ull, row_sp->GetOffset());
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EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_r1_ppc64le);
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EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
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EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
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EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_lr_ppc64le, regloc));
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EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
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EXPECT_EQ(16, regloc.GetOffset());
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// 3: CFA=sp+112 => fp=[CFA-8] lr=[CFA+16]
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row_sp = unwind_plan.GetRowForFunctionOffset(24);
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EXPECT_EQ(24ull, row_sp->GetOffset());
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EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_r1_ppc64le);
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EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
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EXPECT_EQ(112, row_sp->GetCFAValue().GetOffset());
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EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_r31_ppc64le, regloc));
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EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
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EXPECT_EQ(-8, regloc.GetOffset());
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EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_lr_ppc64le, regloc));
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EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
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EXPECT_EQ(16, regloc.GetOffset());
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// 4: CFA=r31+112 => fp=[CFA-8] lr=[CFA+16]
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row_sp = unwind_plan.GetRowForFunctionOffset(28);
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EXPECT_EQ(28ull, row_sp->GetOffset());
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EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_r31_ppc64le);
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EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
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EXPECT_EQ(112, row_sp->GetCFAValue().GetOffset());
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EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_r31_ppc64le, regloc));
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EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
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EXPECT_EQ(-8, regloc.GetOffset());
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EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_lr_ppc64le, regloc));
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EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
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EXPECT_EQ(16, regloc.GetOffset());
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// 5: CFA=sp+0 => fp=[CFA-8] lr=[CFA+16]
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row_sp = unwind_plan.GetRowForFunctionOffset(40);
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EXPECT_EQ(40ull, row_sp->GetOffset());
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EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_r1_ppc64le);
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EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
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EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
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EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_r31_ppc64le, regloc));
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EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
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EXPECT_EQ(-8, regloc.GetOffset());
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EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_lr_ppc64le, regloc));
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EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
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EXPECT_EQ(16, regloc.GetOffset());
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}
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TEST_F(TestPPC64InstEmulation, TestMediumFunction) {
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ArchSpec arch("powerpc64le-linux-gnu");
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std::unique_ptr<UnwindAssemblyInstEmulation> engine(
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static_cast<UnwindAssemblyInstEmulation *>(
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UnwindAssemblyInstEmulation::CreateInstance(arch)));
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ASSERT_NE(nullptr, engine);
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UnwindPlan::RowSP row_sp;
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AddressRange sample_range;
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UnwindPlan unwind_plan(eRegisterKindLLDB);
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UnwindPlan::Row::RegisterLocation regloc;
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// prologue and epilogue of main() (call-func.c),
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// with several calls and stack variables.
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//
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// compiled with clang -O0 -g
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uint8_t data[] = {
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// prologue
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0xa6, 0x02, 0x08, 0x7c, // 0: mflr r0
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0xf8, 0xff, 0xe1, 0xfb, // 4: std r31, -8(r1)
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0x10, 0x00, 0x01, 0xf8, // 8: std r0, 16(r1)
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0x78, 0x0b, 0x3e, 0x7c, // 12: mr r30, r1
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0xe0, 0x06, 0x20, 0x78, // 16: clrldi r0, r1, 59
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0xa0, 0xfa, 0x00, 0x20, // 20: subfic r0, r0, -1376
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0x6a, 0x01, 0x21, 0x7c, // 24: stdux r1, r1, r0
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0x78, 0x0b, 0x3f, 0x7c, // 28: mr r31, r1
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// epilogue
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0x00, 0x00, 0x21, 0xe8, // 32: ld r1, 0(r1)
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0x20, 0x00, 0x80, 0x4e // 36: blr
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};
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sample_range = AddressRange(0x1000, sizeof(data));
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EXPECT_TRUE(engine->GetNonCallSiteUnwindPlanFromAssembly(
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sample_range, data, sizeof(data), unwind_plan));
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// 0: CFA=sp+0
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row_sp = unwind_plan.GetRowForFunctionOffset(0);
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EXPECT_EQ(0ull, row_sp->GetOffset());
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EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_r1_ppc64le);
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EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
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EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
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// 1: CFA=sp+0 => fp=[CFA-8]
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row_sp = unwind_plan.GetRowForFunctionOffset(8);
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EXPECT_EQ(8ull, row_sp->GetOffset());
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EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_r1_ppc64le);
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EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
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EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
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EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_r31_ppc64le, regloc));
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EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
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EXPECT_EQ(-8, regloc.GetOffset());
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// 2: CFA=sp+0 => fp=[CFA-8] lr=[CFA+16]
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row_sp = unwind_plan.GetRowForFunctionOffset(12);
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EXPECT_EQ(12ull, row_sp->GetOffset());
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EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_r1_ppc64le);
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EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
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EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
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EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_lr_ppc64le, regloc));
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EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
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EXPECT_EQ(16, regloc.GetOffset());
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// 3: CFA=r30
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row_sp = unwind_plan.GetRowForFunctionOffset(16);
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EXPECT_EQ(16ull, row_sp->GetOffset());
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EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_r30_ppc64le);
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EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
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EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
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row_sp = unwind_plan.GetRowForFunctionOffset(32);
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EXPECT_EQ(16ull, row_sp->GetOffset());
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EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_r30_ppc64le);
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EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
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EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
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// 4: CFA=sp+0
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row_sp = unwind_plan.GetRowForFunctionOffset(36);
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EXPECT_EQ(36ull, row_sp->GetOffset());
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EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_r1_ppc64le);
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EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
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EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
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}
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