forked from OSchip/llvm-project
626 lines
25 KiB
C++
626 lines
25 KiB
C++
// Test target codegen - host bc file has to be created first.
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
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// RUN: %clang_cc1 -verify -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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// Check that the execution mode of all 6 target regions is set to Generic Mode.
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// CHECK-DAG: {{@__omp_offloading_.+l100}}_exec_mode = weak constant i8 1
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// CHECK-DAG: {{@__omp_offloading_.+l177}}_exec_mode = weak constant i8 1
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// CHECK-DAG: {{@__omp_offloading_.+l287}}_exec_mode = weak constant i8 1
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// CHECK-DAG: {{@__omp_offloading_.+l324}}_exec_mode = weak constant i8 1
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// CHECK-DAG: {{@__omp_offloading_.+l342}}_exec_mode = weak constant i8 1
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// CHECK-DAG: {{@__omp_offloading_.+l307}}_exec_mode = weak constant i8 1
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__thread int id;
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template<typename tx, typename ty>
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struct TT{
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tx X;
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ty Y;
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};
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int foo(int n) {
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int a = 0;
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short aa = 0;
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float b[10];
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float bn[n];
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double c[5][10];
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double cn[5][n];
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TT<long long, char> d;
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// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+foo.+l100}}_worker()
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// CHECK-DAG: [[OMP_EXEC_STATUS:%.+]] = alloca i8,
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// CHECK-DAG: [[OMP_WORK_FN:%.+]] = alloca i8*,
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// CHECK: store i8* null, i8** [[OMP_WORK_FN]],
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// CHECK: store i8 0, i8* [[OMP_EXEC_STATUS]],
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// CHECK: br label {{%?}}[[AWAIT_WORK:.+]]
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//
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// CHECK: [[AWAIT_WORK]]
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// CHECK: call void @llvm.nvvm.barrier0()
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// CHECK: [[WORK:%.+]] = load i8*, i8** [[OMP_WORK_FN]],
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// CHECK: [[SHOULD_EXIT:%.+]] = icmp eq i8* [[WORK]], null
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// CHECK: br i1 [[SHOULD_EXIT]], label {{%?}}[[EXIT:.+]], label {{%?}}[[SEL_WORKERS:.+]]
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//
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// CHECK: [[SEL_WORKERS]]
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// CHECK: [[ST:%.+]] = load i8, i8* [[OMP_EXEC_STATUS]],
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// CHECK: [[IS_ACTIVE:%.+]] = icmp ne i8 [[ST]], 0
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// CHECK: br i1 [[IS_ACTIVE]], label {{%?}}[[EXEC_PARALLEL:.+]], label {{%?}}[[BAR_PARALLEL:.+]]
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//
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// CHECK: [[EXEC_PARALLEL]]
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// CHECK: br label {{%?}}[[TERM_PARALLEL:.+]]
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//
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// CHECK: [[TERM_PARALLEL]]
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// CHECK: br label {{%?}}[[BAR_PARALLEL]]
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//
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// CHECK: [[BAR_PARALLEL]]
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// CHECK: call void @llvm.nvvm.barrier0()
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// CHECK: br label {{%?}}[[AWAIT_WORK]]
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//
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// CHECK: [[EXIT]]
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// CHECK: ret void
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// CHECK: define {{.*}}void [[T1:@__omp_offloading_.+foo.+l100]]()
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// CHECK-DAG: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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// CHECK-DAG: [[NTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK-DAG: [[WS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
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// CHECK-DAG: [[TH_LIMIT:%.+]] = sub i32 [[NTH]], [[WS]]
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// CHECK: [[IS_WORKER:%.+]] = icmp ult i32 [[TID]], [[TH_LIMIT]]
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// CHECK: br i1 [[IS_WORKER]], label {{%?}}[[WORKER:.+]], label {{%?}}[[CHECK_MASTER:.+]]
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//
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// CHECK: [[WORKER]]
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// CHECK: {{call|invoke}} void [[T1]]_worker()
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// CHECK: br label {{%?}}[[EXIT:.+]]
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//
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// CHECK: [[CHECK_MASTER]]
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// CHECK-DAG: [[CMTID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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// CHECK-DAG: [[CMNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK-DAG: [[CMWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
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// CHECK: [[IS_MASTER:%.+]] = icmp eq i32 [[CMTID]],
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// CHECK: br i1 [[IS_MASTER]], label {{%?}}[[MASTER:.+]], label {{%?}}[[EXIT]]
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//
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// CHECK: [[MASTER]]
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// CHECK-DAG: [[MNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK-DAG: [[MWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
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// CHECK: [[MTMP1:%.+]] = sub i32 [[MNTH]], [[MWS]]
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// CHECK: call void @__kmpc_kernel_init(i32 [[MTMP1]]
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// CHECK: br label {{%?}}[[TERMINATE:.+]]
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//
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// CHECK: [[TERMINATE]]
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// CHECK: call void @__kmpc_kernel_deinit()
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// CHECK: call void @llvm.nvvm.barrier0()
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// CHECK: br label {{%?}}[[EXIT]]
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//
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// CHECK: [[EXIT]]
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// CHECK: ret void
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#pragma omp target
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{
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}
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// CHECK-NOT: define {{.*}}void [[T2:@__omp_offloading_.+foo.+]]_worker()
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#pragma omp target if(0)
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{
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}
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// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+foo.+l177}}_worker()
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// CHECK-DAG: [[OMP_EXEC_STATUS:%.+]] = alloca i8,
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// CHECK-DAG: [[OMP_WORK_FN:%.+]] = alloca i8*,
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// CHECK: store i8* null, i8** [[OMP_WORK_FN]],
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// CHECK: store i8 0, i8* [[OMP_EXEC_STATUS]],
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// CHECK: br label {{%?}}[[AWAIT_WORK:.+]]
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//
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// CHECK: [[AWAIT_WORK]]
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// CHECK: call void @llvm.nvvm.barrier0()
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// CHECK: [[WORK:%.+]] = load i8*, i8** [[OMP_WORK_FN]],
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// CHECK: [[SHOULD_EXIT:%.+]] = icmp eq i8* [[WORK]], null
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// CHECK: br i1 [[SHOULD_EXIT]], label {{%?}}[[EXIT:.+]], label {{%?}}[[SEL_WORKERS:.+]]
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//
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// CHECK: [[SEL_WORKERS]]
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// CHECK: [[ST:%.+]] = load i8, i8* [[OMP_EXEC_STATUS]],
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// CHECK: [[IS_ACTIVE:%.+]] = icmp ne i8 [[ST]], 0
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// CHECK: br i1 [[IS_ACTIVE]], label {{%?}}[[EXEC_PARALLEL:.+]], label {{%?}}[[BAR_PARALLEL:.+]]
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//
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// CHECK: [[EXEC_PARALLEL]]
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// CHECK: br label {{%?}}[[TERM_PARALLEL:.+]]
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//
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// CHECK: [[TERM_PARALLEL]]
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// CHECK: br label {{%?}}[[BAR_PARALLEL]]
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//
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// CHECK: [[BAR_PARALLEL]]
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// CHECK: call void @llvm.nvvm.barrier0()
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// CHECK: br label {{%?}}[[AWAIT_WORK]]
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//
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// CHECK: [[EXIT]]
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// CHECK: ret void
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// CHECK: define {{.*}}void [[T2:@__omp_offloading_.+foo.+l177]](i[[SZ:32|64]] [[ARG1:%[a-zA-Z_]+]], i[[SZ:32|64]] [[ID:%[a-zA-Z_]+]])
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// CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]],
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// CHECK: store i[[SZ]] [[ARG1]], i[[SZ]]* [[AA_ADDR]],
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// CHECK: [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i16*
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// CHECK-DAG: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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// CHECK-DAG: [[NTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK-DAG: [[WS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
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// CHECK-DAG: [[TH_LIMIT:%.+]] = sub i32 [[NTH]], [[WS]]
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// CHECK: [[IS_WORKER:%.+]] = icmp ult i32 [[TID]], [[TH_LIMIT]]
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// CHECK: br i1 [[IS_WORKER]], label {{%?}}[[WORKER:.+]], label {{%?}}[[CHECK_MASTER:.+]]
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//
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// CHECK: [[WORKER]]
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// CHECK: {{call|invoke}} void [[T2]]_worker()
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// CHECK: br label {{%?}}[[EXIT:.+]]
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//
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// CHECK: [[CHECK_MASTER]]
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// CHECK-DAG: [[CMTID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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// CHECK-DAG: [[CMNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK-DAG: [[CMWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
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// CHECK: [[IS_MASTER:%.+]] = icmp eq i32 [[CMTID]],
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// CHECK: br i1 [[IS_MASTER]], label {{%?}}[[MASTER:.+]], label {{%?}}[[EXIT]]
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//
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// CHECK: [[MASTER]]
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// CHECK-DAG: [[MNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK-DAG: [[MWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
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// CHECK: [[MTMP1:%.+]] = sub i32 [[MNTH]], [[MWS]]
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// CHECK: call void @__kmpc_kernel_init(i32 [[MTMP1]]
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// CHECK: load i16, i16* [[AA_CADDR]],
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// CHECK: br label {{%?}}[[TERMINATE:.+]]
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//
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// CHECK: [[TERMINATE]]
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// CHECK: call void @__kmpc_kernel_deinit()
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// CHECK: call void @llvm.nvvm.barrier0()
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// CHECK: br label {{%?}}[[EXIT]]
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//
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// CHECK: [[EXIT]]
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// CHECK: ret void
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#pragma omp target if(1)
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{
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aa += 1;
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id = aa;
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}
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// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+foo.+l287}}_worker()
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// CHECK-DAG: [[OMP_EXEC_STATUS:%.+]] = alloca i8,
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// CHECK-DAG: [[OMP_WORK_FN:%.+]] = alloca i8*,
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// CHECK: store i8* null, i8** [[OMP_WORK_FN]],
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// CHECK: store i8 0, i8* [[OMP_EXEC_STATUS]],
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// CHECK: br label {{%?}}[[AWAIT_WORK:.+]]
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//
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// CHECK: [[AWAIT_WORK]]
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// CHECK: call void @llvm.nvvm.barrier0()
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// CHECK: [[WORK:%.+]] = load i8*, i8** [[OMP_WORK_FN]],
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// CHECK: [[SHOULD_EXIT:%.+]] = icmp eq i8* [[WORK]], null
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// CHECK: br i1 [[SHOULD_EXIT]], label {{%?}}[[EXIT:.+]], label {{%?}}[[SEL_WORKERS:.+]]
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//
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// CHECK: [[SEL_WORKERS]]
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// CHECK: [[ST:%.+]] = load i8, i8* [[OMP_EXEC_STATUS]],
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// CHECK: [[IS_ACTIVE:%.+]] = icmp ne i8 [[ST]], 0
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// CHECK: br i1 [[IS_ACTIVE]], label {{%?}}[[EXEC_PARALLEL:.+]], label {{%?}}[[BAR_PARALLEL:.+]]
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//
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// CHECK: [[EXEC_PARALLEL]]
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// CHECK: br label {{%?}}[[TERM_PARALLEL:.+]]
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//
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// CHECK: [[TERM_PARALLEL]]
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// CHECK: br label {{%?}}[[BAR_PARALLEL]]
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//
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// CHECK: [[BAR_PARALLEL]]
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// CHECK: call void @llvm.nvvm.barrier0()
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// CHECK: br label {{%?}}[[AWAIT_WORK]]
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//
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// CHECK: [[EXIT]]
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// CHECK: ret void
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// CHECK: define {{.*}}void [[T3:@__omp_offloading_.+foo.+l287]](i[[SZ]]
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// Create local storage for each capture.
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// CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]]
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// CHECK: [[LOCAL_B:%.+]] = alloca [10 x float]*
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// CHECK: [[LOCAL_VLA1:%.+]] = alloca i[[SZ]]
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// CHECK: [[LOCAL_BN:%.+]] = alloca float*
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// CHECK: [[LOCAL_C:%.+]] = alloca [5 x [10 x double]]*
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// CHECK: [[LOCAL_VLA2:%.+]] = alloca i[[SZ]]
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// CHECK: [[LOCAL_VLA3:%.+]] = alloca i[[SZ]]
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// CHECK: [[LOCAL_CN:%.+]] = alloca double*
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// CHECK: [[LOCAL_D:%.+]] = alloca [[TT:%.+]]*
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// CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]]
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// CHECK-DAG: store [10 x float]* [[ARG_B:%.+]], [10 x float]** [[LOCAL_B]]
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// CHECK-DAG: store i[[SZ]] [[ARG_VLA1:%.+]], i[[SZ]]* [[LOCAL_VLA1]]
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// CHECK-DAG: store float* [[ARG_BN:%.+]], float** [[LOCAL_BN]]
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// CHECK-DAG: store [5 x [10 x double]]* [[ARG_C:%.+]], [5 x [10 x double]]** [[LOCAL_C]]
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// CHECK-DAG: store i[[SZ]] [[ARG_VLA2:%.+]], i[[SZ]]* [[LOCAL_VLA2]]
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// CHECK-DAG: store i[[SZ]] [[ARG_VLA3:%.+]], i[[SZ]]* [[LOCAL_VLA3]]
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// CHECK-DAG: store double* [[ARG_CN:%.+]], double** [[LOCAL_CN]]
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// CHECK-DAG: store [[TT]]* [[ARG_D:%.+]], [[TT]]** [[LOCAL_D]]
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//
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// CHECK-64-DAG: [[REF_A:%.+]] = bitcast i64* [[LOCAL_A]] to i32*
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// CHECK-DAG: [[REF_B:%.+]] = load [10 x float]*, [10 x float]** [[LOCAL_B]],
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// CHECK-DAG: [[VAL_VLA1:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA1]],
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// CHECK-DAG: [[REF_BN:%.+]] = load float*, float** [[LOCAL_BN]],
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// CHECK-DAG: [[REF_C:%.+]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[LOCAL_C]],
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// CHECK-DAG: [[VAL_VLA2:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA2]],
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// CHECK-DAG: [[VAL_VLA3:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA3]],
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// CHECK-DAG: [[REF_CN:%.+]] = load double*, double** [[LOCAL_CN]],
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// CHECK-DAG: [[REF_D:%.+]] = load [[TT]]*, [[TT]]** [[LOCAL_D]],
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//
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// CHECK-DAG: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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// CHECK-DAG: [[NTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK-DAG: [[WS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
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// CHECK-DAG: [[TH_LIMIT:%.+]] = sub i32 [[NTH]], [[WS]]
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// CHECK: [[IS_WORKER:%.+]] = icmp ult i32 [[TID]], [[TH_LIMIT]]
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// CHECK: br i1 [[IS_WORKER]], label {{%?}}[[WORKER:.+]], label {{%?}}[[CHECK_MASTER:.+]]
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//
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// CHECK: [[WORKER]]
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// CHECK: {{call|invoke}} void [[T3]]_worker()
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// CHECK: br label {{%?}}[[EXIT:.+]]
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//
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// CHECK: [[CHECK_MASTER]]
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// CHECK-DAG: [[CMTID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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// CHECK-DAG: [[CMNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK-DAG: [[CMWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
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// CHECK: [[IS_MASTER:%.+]] = icmp eq i32 [[CMTID]],
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// CHECK: br i1 [[IS_MASTER]], label {{%?}}[[MASTER:.+]], label {{%?}}[[EXIT]]
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//
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// CHECK: [[MASTER]]
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// CHECK-DAG: [[MNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK-DAG: [[MWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
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// CHECK: [[MTMP1:%.+]] = sub i32 [[MNTH]], [[MWS]]
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// CHECK: call void @__kmpc_kernel_init(i32 [[MTMP1]]
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//
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// Use captures.
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// CHECK-64-DAG: load i32, i32* [[REF_A]]
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// CHECK-32-DAG: load i32, i32* [[LOCAL_A]]
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// CHECK-DAG: getelementptr inbounds [10 x float], [10 x float]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2
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// CHECK-DAG: getelementptr inbounds float, float* [[REF_BN]], i[[SZ]] 3
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// CHECK-DAG: getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[REF_C]], i[[SZ]] 0, i[[SZ]] 1
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// CHECK-DAG: getelementptr inbounds double, double* [[REF_CN]], i[[SZ]] %{{.+}}
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// CHECK-DAG: getelementptr inbounds [[TT]], [[TT]]* [[REF_D]], i32 0, i32 0
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//
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// CHECK: br label {{%?}}[[TERMINATE:.+]]
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//
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// CHECK: [[TERMINATE]]
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// CHECK: call void @__kmpc_kernel_deinit()
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// CHECK: call void @llvm.nvvm.barrier0()
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// CHECK: br label {{%?}}[[EXIT]]
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//
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// CHECK: [[EXIT]]
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// CHECK: ret void
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#pragma omp target if(n>20)
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{
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a += 1;
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b[2] += 1.0;
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bn[3] += 1.0;
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c[1][2] += 1.0;
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cn[1][3] += 1.0;
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d.X += 1;
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d.Y += 1;
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}
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return a;
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}
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template<typename tx>
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tx ftemplate(int n) {
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tx a = 0;
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short aa = 0;
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tx b[10];
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#pragma omp target if(n>40)
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{
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a += 1;
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aa += 1;
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b[2] += 1;
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}
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return a;
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}
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static
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int fstatic(int n) {
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int a = 0;
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short aa = 0;
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char aaa = 0;
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int b[10];
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#pragma omp target if(n>50)
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{
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a += 1;
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aa += 1;
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aaa += 1;
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b[2] += 1;
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}
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return a;
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}
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struct S1 {
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double a;
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int r1(int n){
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int b = n+1;
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short int c[2][n];
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#pragma omp target if(n>60)
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{
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this->a = (double)b + 1.5;
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c[1][1] = ++a;
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}
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return c[1][1] + (int)b;
|
|
}
|
|
};
|
|
|
|
int bar(int n){
|
|
int a = 0;
|
|
|
|
a += foo(n);
|
|
|
|
S1 S;
|
|
a += S.r1(n);
|
|
|
|
a += fstatic(n);
|
|
|
|
a += ftemplate<int>(n);
|
|
|
|
return a;
|
|
}
|
|
|
|
// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+static.+324}}_worker()
|
|
// CHECK-DAG: [[OMP_EXEC_STATUS:%.+]] = alloca i8,
|
|
// CHECK-DAG: [[OMP_WORK_FN:%.+]] = alloca i8*,
|
|
// CHECK: store i8* null, i8** [[OMP_WORK_FN]],
|
|
// CHECK: store i8 0, i8* [[OMP_EXEC_STATUS]],
|
|
// CHECK: br label {{%?}}[[AWAIT_WORK:.+]]
|
|
//
|
|
// CHECK: [[AWAIT_WORK]]
|
|
// CHECK: call void @llvm.nvvm.barrier0()
|
|
// CHECK: [[WORK:%.+]] = load i8*, i8** [[OMP_WORK_FN]],
|
|
// CHECK: [[SHOULD_EXIT:%.+]] = icmp eq i8* [[WORK]], null
|
|
// CHECK: br i1 [[SHOULD_EXIT]], label {{%?}}[[EXIT:.+]], label {{%?}}[[SEL_WORKERS:.+]]
|
|
//
|
|
// CHECK: [[SEL_WORKERS]]
|
|
// CHECK: [[ST:%.+]] = load i8, i8* [[OMP_EXEC_STATUS]],
|
|
// CHECK: [[IS_ACTIVE:%.+]] = icmp ne i8 [[ST]], 0
|
|
// CHECK: br i1 [[IS_ACTIVE]], label {{%?}}[[EXEC_PARALLEL:.+]], label {{%?}}[[BAR_PARALLEL:.+]]
|
|
//
|
|
// CHECK: [[EXEC_PARALLEL]]
|
|
// CHECK: br label {{%?}}[[TERM_PARALLEL:.+]]
|
|
//
|
|
// CHECK: [[TERM_PARALLEL]]
|
|
// CHECK: br label {{%?}}[[BAR_PARALLEL]]
|
|
//
|
|
// CHECK: [[BAR_PARALLEL]]
|
|
// CHECK: call void @llvm.nvvm.barrier0()
|
|
// CHECK: br label {{%?}}[[AWAIT_WORK]]
|
|
//
|
|
// CHECK: [[EXIT]]
|
|
// CHECK: ret void
|
|
|
|
// CHECK: define {{.*}}void [[T4:@__omp_offloading_.+static.+l324]](i[[SZ]]
|
|
// Create local storage for each capture.
|
|
// CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]]
|
|
// CHECK: [[LOCAL_AA:%.+]] = alloca i[[SZ]]
|
|
// CHECK: [[LOCAL_AAA:%.+]] = alloca i[[SZ]]
|
|
// CHECK: [[LOCAL_B:%.+]] = alloca [10 x i32]*
|
|
// CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]]
|
|
// CHECK-DAG: store i[[SZ]] [[ARG_AA:%.+]], i[[SZ]]* [[LOCAL_AA]]
|
|
// CHECK-DAG: store i[[SZ]] [[ARG_AAA:%.+]], i[[SZ]]* [[LOCAL_AAA]]
|
|
// CHECK-DAG: store [10 x i32]* [[ARG_B:%.+]], [10 x i32]** [[LOCAL_B]]
|
|
// Store captures in the context.
|
|
// CHECK-64-DAG: [[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32*
|
|
// CHECK-DAG: [[REF_AA:%.+]] = bitcast i[[SZ]]* [[LOCAL_AA]] to i16*
|
|
// CHECK-DAG: [[REF_AAA:%.+]] = bitcast i[[SZ]]* [[LOCAL_AAA]] to i8*
|
|
// CHECK-DAG: [[REF_B:%.+]] = load [10 x i32]*, [10 x i32]** [[LOCAL_B]],
|
|
//
|
|
// CHECK-DAG: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
|
|
// CHECK-DAG: [[NTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
|
|
// CHECK-DAG: [[WS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
|
|
// CHECK-DAG: [[TH_LIMIT:%.+]] = sub i32 [[NTH]], [[WS]]
|
|
// CHECK: [[IS_WORKER:%.+]] = icmp ult i32 [[TID]], [[TH_LIMIT]]
|
|
// CHECK: br i1 [[IS_WORKER]], label {{%?}}[[WORKER:.+]], label {{%?}}[[CHECK_MASTER:.+]]
|
|
//
|
|
// CHECK: [[WORKER]]
|
|
// CHECK: {{call|invoke}} void [[T4]]_worker()
|
|
// CHECK: br label {{%?}}[[EXIT:.+]]
|
|
//
|
|
// CHECK: [[CHECK_MASTER]]
|
|
// CHECK-DAG: [[CMTID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
|
|
// CHECK-DAG: [[CMNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
|
|
// CHECK-DAG: [[CMWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
|
|
// CHECK: [[IS_MASTER:%.+]] = icmp eq i32 [[CMTID]],
|
|
// CHECK: br i1 [[IS_MASTER]], label {{%?}}[[MASTER:.+]], label {{%?}}[[EXIT]]
|
|
//
|
|
// CHECK: [[MASTER]]
|
|
// CHECK-DAG: [[MNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
|
|
// CHECK-DAG: [[MWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
|
|
// CHECK: [[MTMP1:%.+]] = sub i32 [[MNTH]], [[MWS]]
|
|
// CHECK: call void @__kmpc_kernel_init(i32 [[MTMP1]]
|
|
// CHECK-64-DAG: load i32, i32* [[REF_A]]
|
|
// CHECK-32-DAG: load i32, i32* [[LOCAL_A]]
|
|
// CHECK-DAG: load i16, i16* [[REF_AA]]
|
|
// CHECK-DAG: getelementptr inbounds [10 x i32], [10 x i32]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2
|
|
// CHECK: br label {{%?}}[[TERMINATE:.+]]
|
|
//
|
|
// CHECK: [[TERMINATE]]
|
|
// CHECK: call void @__kmpc_kernel_deinit()
|
|
// CHECK: call void @llvm.nvvm.barrier0()
|
|
// CHECK: br label {{%?}}[[EXIT]]
|
|
//
|
|
// CHECK: [[EXIT]]
|
|
// CHECK: ret void
|
|
|
|
|
|
|
|
// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+S1.+l342}}_worker()
|
|
// CHECK-DAG: [[OMP_EXEC_STATUS:%.+]] = alloca i8,
|
|
// CHECK-DAG: [[OMP_WORK_FN:%.+]] = alloca i8*,
|
|
// CHECK: store i8* null, i8** [[OMP_WORK_FN]],
|
|
// CHECK: store i8 0, i8* [[OMP_EXEC_STATUS]],
|
|
// CHECK: br label {{%?}}[[AWAIT_WORK:.+]]
|
|
//
|
|
// CHECK: [[AWAIT_WORK]]
|
|
// CHECK: call void @llvm.nvvm.barrier0()
|
|
// CHECK: [[WORK:%.+]] = load i8*, i8** [[OMP_WORK_FN]],
|
|
// CHECK: [[SHOULD_EXIT:%.+]] = icmp eq i8* [[WORK]], null
|
|
// CHECK: br i1 [[SHOULD_EXIT]], label {{%?}}[[EXIT:.+]], label {{%?}}[[SEL_WORKERS:.+]]
|
|
//
|
|
// CHECK: [[SEL_WORKERS]]
|
|
// CHECK: [[ST:%.+]] = load i8, i8* [[OMP_EXEC_STATUS]],
|
|
// CHECK: [[IS_ACTIVE:%.+]] = icmp ne i8 [[ST]], 0
|
|
// CHECK: br i1 [[IS_ACTIVE]], label {{%?}}[[EXEC_PARALLEL:.+]], label {{%?}}[[BAR_PARALLEL:.+]]
|
|
//
|
|
// CHECK: [[EXEC_PARALLEL]]
|
|
// CHECK: br label {{%?}}[[TERM_PARALLEL:.+]]
|
|
//
|
|
// CHECK: [[TERM_PARALLEL]]
|
|
// CHECK: br label {{%?}}[[BAR_PARALLEL]]
|
|
//
|
|
// CHECK: [[BAR_PARALLEL]]
|
|
// CHECK: call void @llvm.nvvm.barrier0()
|
|
// CHECK: br label {{%?}}[[AWAIT_WORK]]
|
|
//
|
|
// CHECK: [[EXIT]]
|
|
// CHECK: ret void
|
|
|
|
// CHECK: define {{.*}}void [[T5:@__omp_offloading_.+S1.+l342]](
|
|
// Create local storage for each capture.
|
|
// CHECK: [[LOCAL_THIS:%.+]] = alloca [[S1:%struct.*]]*
|
|
// CHECK: [[LOCAL_B:%.+]] = alloca i[[SZ]]
|
|
// CHECK: [[LOCAL_VLA1:%.+]] = alloca i[[SZ]]
|
|
// CHECK: [[LOCAL_VLA2:%.+]] = alloca i[[SZ]]
|
|
// CHECK: [[LOCAL_C:%.+]] = alloca i16*
|
|
// CHECK-DAG: store [[S1]]* [[ARG_THIS:%.+]], [[S1]]** [[LOCAL_THIS]]
|
|
// CHECK-DAG: store i[[SZ]] [[ARG_B:%.+]], i[[SZ]]* [[LOCAL_B]]
|
|
// CHECK-DAG: store i[[SZ]] [[ARG_VLA1:%.+]], i[[SZ]]* [[LOCAL_VLA1]]
|
|
// CHECK-DAG: store i[[SZ]] [[ARG_VLA2:%.+]], i[[SZ]]* [[LOCAL_VLA2]]
|
|
// CHECK-DAG: store i16* [[ARG_C:%.+]], i16** [[LOCAL_C]]
|
|
// Store captures in the context.
|
|
// CHECK-DAG: [[REF_THIS:%.+]] = load [[S1]]*, [[S1]]** [[LOCAL_THIS]],
|
|
// CHECK-64-DAG:[[REF_B:%.+]] = bitcast i[[SZ]]* [[LOCAL_B]] to i32*
|
|
// CHECK-DAG: [[VAL_VLA1:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA1]],
|
|
// CHECK-DAG: [[VAL_VLA2:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA2]],
|
|
// CHECK-DAG: [[REF_C:%.+]] = load i16*, i16** [[LOCAL_C]],
|
|
//
|
|
// CHECK-DAG: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
|
|
// CHECK-DAG: [[NTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
|
|
// CHECK-DAG: [[WS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
|
|
// CHECK-DAG: [[TH_LIMIT:%.+]] = sub i32 [[NTH]], [[WS]]
|
|
// CHECK: [[IS_WORKER:%.+]] = icmp ult i32 [[TID]], [[TH_LIMIT]]
|
|
// CHECK: br i1 [[IS_WORKER]], label {{%?}}[[WORKER:.+]], label {{%?}}[[CHECK_MASTER:.+]]
|
|
//
|
|
// CHECK: [[WORKER]]
|
|
// CHECK: {{call|invoke}} void [[T5]]_worker()
|
|
// CHECK: br label {{%?}}[[EXIT:.+]]
|
|
//
|
|
// CHECK: [[CHECK_MASTER]]
|
|
// CHECK-DAG: [[CMTID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
|
|
// CHECK-DAG: [[CMNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
|
|
// CHECK-DAG: [[CMWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
|
|
// CHECK: [[IS_MASTER:%.+]] = icmp eq i32 [[CMTID]],
|
|
// CHECK: br i1 [[IS_MASTER]], label {{%?}}[[MASTER:.+]], label {{%?}}[[EXIT]]
|
|
//
|
|
// CHECK: [[MASTER]]
|
|
// CHECK-DAG: [[MNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
|
|
// CHECK-DAG: [[MWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
|
|
// CHECK: [[MTMP1:%.+]] = sub i32 [[MNTH]], [[MWS]]
|
|
// CHECK: call void @__kmpc_kernel_init(i32 [[MTMP1]]
|
|
// Use captures.
|
|
// CHECK-DAG: getelementptr inbounds [[S1]], [[S1]]* [[REF_THIS]], i32 0, i32 0
|
|
// CHECK-64-DAG:load i32, i32* [[REF_B]]
|
|
// CHECK-32-DAG:load i32, i32* [[LOCAL_B]]
|
|
// CHECK-DAG: getelementptr inbounds i16, i16* [[REF_C]], i[[SZ]] %{{.+}}
|
|
// CHECK: br label {{%?}}[[TERMINATE:.+]]
|
|
//
|
|
// CHECK: [[TERMINATE]]
|
|
// CHECK: call void @__kmpc_kernel_deinit()
|
|
// CHECK: call void @llvm.nvvm.barrier0()
|
|
// CHECK: br label {{%?}}[[EXIT]]
|
|
//
|
|
// CHECK: [[EXIT]]
|
|
// CHECK: ret void
|
|
|
|
|
|
|
|
// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l307}}_worker()
|
|
// CHECK-DAG: [[OMP_EXEC_STATUS:%.+]] = alloca i8,
|
|
// CHECK-DAG: [[OMP_WORK_FN:%.+]] = alloca i8*,
|
|
// CHECK: store i8* null, i8** [[OMP_WORK_FN]],
|
|
// CHECK: store i8 0, i8* [[OMP_EXEC_STATUS]],
|
|
// CHECK: br label {{%?}}[[AWAIT_WORK:.+]]
|
|
//
|
|
// CHECK: [[AWAIT_WORK]]
|
|
// CHECK: call void @llvm.nvvm.barrier0()
|
|
// CHECK: [[WORK:%.+]] = load i8*, i8** [[OMP_WORK_FN]],
|
|
// CHECK: [[SHOULD_EXIT:%.+]] = icmp eq i8* [[WORK]], null
|
|
// CHECK: br i1 [[SHOULD_EXIT]], label {{%?}}[[EXIT:.+]], label {{%?}}[[SEL_WORKERS:.+]]
|
|
//
|
|
// CHECK: [[SEL_WORKERS]]
|
|
// CHECK: [[ST:%.+]] = load i8, i8* [[OMP_EXEC_STATUS]],
|
|
// CHECK: [[IS_ACTIVE:%.+]] = icmp ne i8 [[ST]], 0
|
|
// CHECK: br i1 [[IS_ACTIVE]], label {{%?}}[[EXEC_PARALLEL:.+]], label {{%?}}[[BAR_PARALLEL:.+]]
|
|
//
|
|
// CHECK: [[EXEC_PARALLEL]]
|
|
// CHECK: br label {{%?}}[[TERM_PARALLEL:.+]]
|
|
//
|
|
// CHECK: [[TERM_PARALLEL]]
|
|
// CHECK: br label {{%?}}[[BAR_PARALLEL]]
|
|
//
|
|
// CHECK: [[BAR_PARALLEL]]
|
|
// CHECK: call void @llvm.nvvm.barrier0()
|
|
// CHECK: br label {{%?}}[[AWAIT_WORK]]
|
|
//
|
|
// CHECK: [[EXIT]]
|
|
// CHECK: ret void
|
|
|
|
// CHECK: define {{.*}}void [[T6:@__omp_offloading_.+template.+l307]](i[[SZ]]
|
|
// Create local storage for each capture.
|
|
// CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]]
|
|
// CHECK: [[LOCAL_AA:%.+]] = alloca i[[SZ]]
|
|
// CHECK: [[LOCAL_B:%.+]] = alloca [10 x i32]*
|
|
// CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]]
|
|
// CHECK-DAG: store i[[SZ]] [[ARG_AA:%.+]], i[[SZ]]* [[LOCAL_AA]]
|
|
// CHECK-DAG: store [10 x i32]* [[ARG_B:%.+]], [10 x i32]** [[LOCAL_B]]
|
|
// Store captures in the context.
|
|
// CHECK-64-DAG:[[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32*
|
|
// CHECK-DAG: [[REF_AA:%.+]] = bitcast i[[SZ]]* [[LOCAL_AA]] to i16*
|
|
// CHECK-DAG: [[REF_B:%.+]] = load [10 x i32]*, [10 x i32]** [[LOCAL_B]],
|
|
//
|
|
// CHECK-DAG: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
|
|
// CHECK-DAG: [[NTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
|
|
// CHECK-DAG: [[WS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
|
|
// CHECK-DAG: [[TH_LIMIT:%.+]] = sub i32 [[NTH]], [[WS]]
|
|
// CHECK: [[IS_WORKER:%.+]] = icmp ult i32 [[TID]], [[TH_LIMIT]]
|
|
// CHECK: br i1 [[IS_WORKER]], label {{%?}}[[WORKER:.+]], label {{%?}}[[CHECK_MASTER:.+]]
|
|
//
|
|
// CHECK: [[WORKER]]
|
|
// CHECK: {{call|invoke}} void [[T6]]_worker()
|
|
// CHECK: br label {{%?}}[[EXIT:.+]]
|
|
//
|
|
// CHECK: [[CHECK_MASTER]]
|
|
// CHECK-DAG: [[CMTID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
|
|
// CHECK-DAG: [[CMNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
|
|
// CHECK-DAG: [[CMWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
|
|
// CHECK: [[IS_MASTER:%.+]] = icmp eq i32 [[CMTID]],
|
|
// CHECK: br i1 [[IS_MASTER]], label {{%?}}[[MASTER:.+]], label {{%?}}[[EXIT]]
|
|
//
|
|
// CHECK: [[MASTER]]
|
|
// CHECK-DAG: [[MNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
|
|
// CHECK-DAG: [[MWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
|
|
// CHECK: [[MTMP1:%.+]] = sub i32 [[MNTH]], [[MWS]]
|
|
// CHECK: call void @__kmpc_kernel_init(i32 [[MTMP1]]
|
|
//
|
|
// CHECK-64-DAG: load i32, i32* [[REF_A]]
|
|
// CHECK-32-DAG: load i32, i32* [[LOCAL_A]]
|
|
// CHECK-DAG: load i16, i16* [[REF_AA]]
|
|
// CHECK-DAG: getelementptr inbounds [10 x i32], [10 x i32]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2
|
|
//
|
|
// CHECK: br label {{%?}}[[TERMINATE:.+]]
|
|
//
|
|
// CHECK: [[TERMINATE]]
|
|
// CHECK: call void @__kmpc_kernel_deinit()
|
|
// CHECK: call void @llvm.nvvm.barrier0()
|
|
// CHECK: br label {{%?}}[[EXIT]]
|
|
//
|
|
// CHECK: [[EXIT]]
|
|
// CHECK: ret void
|
|
#endif
|