forked from OSchip/llvm-project
81 lines
2.8 KiB
LLVM
81 lines
2.8 KiB
LLVM
; RUN: opt -basicaa -loop-rotate -licm -instcombine -indvars -loop-unroll -S %s | FileCheck %s
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;
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; PR18361: ScalarEvolution::getAddRecExpr():
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; Assertion `isLoopInvariant(Operands[i],...
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;
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; After a series of loop optimizations, SCEV's LoopDispositions grow stale.
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; In particular, LoopSimplify hoists %cmp4, resulting in this SCEV for %add:
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; {(zext i1 %cmp4 to i32),+,1}<nw><%for.cond1.preheader>
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;
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; When recomputing the SCEV for %ashr, we truncate the operands to get:
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; (zext i1 %cmp4 to i16)
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;
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; This SCEV was never mapped to a value so never invalidated. It's
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; loop disposition is still marked as non-loop-invariant, which is
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; inconsistent with the AddRec.
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target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx"
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@d = common global i32 0, align 4
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@a = common global i32 0, align 4
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@c = common global i32 0, align 4
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@b = common global i32 0, align 4
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; Check that the def-use chain that leads to the bad SCEV is still
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; there.
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;
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; CHECK-LABEL: @foo
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; CHECK-LABEL: entry:
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; CHECK-LABEL: for.cond1.preheader:
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; CHECK-LABEL: for.body3:
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; CHECK: %cmp4.le.le
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; CHECK: %conv.le.le = zext i1 %cmp4.le.le to i32
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; CHECK: %xor.le.le = xor i32 %conv6.le.le, 1
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define void @foo() {
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entry:
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br label %for.cond
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for.cond: ; preds = %for.inc7, %entry
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%storemerge = phi i32 [ 0, %entry ], [ %inc8, %for.inc7 ]
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%f.0 = phi i32 [ undef, %entry ], [ %f.1, %for.inc7 ]
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store i32 %storemerge, i32* @d, align 4
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%cmp = icmp slt i32 %storemerge, 1
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br i1 %cmp, label %for.cond1, label %for.end9
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for.cond1: ; preds = %for.cond, %for.body3
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%storemerge1 = phi i32 [ %inc, %for.body3 ], [ 0, %for.cond ]
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%f.1 = phi i32 [ %xor, %for.body3 ], [ %f.0, %for.cond ]
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store i32 %storemerge1, i32* @a, align 4
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%cmp2 = icmp slt i32 %storemerge1, 1
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br i1 %cmp2, label %for.body3, label %for.inc7
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for.body3: ; preds = %for.cond1
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%0 = load i32, i32* @c, align 4
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%cmp4 = icmp sge i32 %storemerge1, %0
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%conv = zext i1 %cmp4 to i32
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%1 = load i32, i32* @d, align 4
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%add = add nsw i32 %conv, %1
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%sext = shl i32 %add, 16
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%conv6 = ashr exact i32 %sext, 16
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%xor = xor i32 %conv6, 1
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%inc = add nsw i32 %storemerge1, 1
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br label %for.cond1
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for.inc7: ; preds = %for.cond1
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%2 = load i32, i32* @d, align 4
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%inc8 = add nsw i32 %2, 1
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br label %for.cond
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for.end9: ; preds = %for.cond
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%cmp10 = icmp sgt i32 %f.0, 0
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br i1 %cmp10, label %if.then, label %if.end
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if.then: ; preds = %for.end9
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store i32 0, i32* @b, align 4
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br label %if.end
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if.end: ; preds = %if.then, %for.end9
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ret void
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}
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