forked from OSchip/llvm-project
240 lines
6.1 KiB
LLVM
240 lines
6.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instsimplify -S | FileCheck %s
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define i47 @shl_by_0(i47 %A) {
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; CHECK-LABEL: @shl_by_0(
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; CHECK-NEXT: ret i47 [[A:%.*]]
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;
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%B = shl i47 %A, 0
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ret i47 %B
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}
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define i41 @shl_0(i41 %X) {
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; CHECK-LABEL: @shl_0(
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; CHECK-NEXT: ret i41 0
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;
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%B = shl i41 0, %X
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ret i41 %B
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}
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define <2 x i41> @shl_0_vec_undef_elt(<2 x i41> %X) {
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; CHECK-LABEL: @shl_0_vec_undef_elt(
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; CHECK-NEXT: ret <2 x i41> zeroinitializer
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;
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%B = shl <2 x i41> <i41 0, i41 undef>, %X
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ret <2 x i41> %B
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}
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define i41 @ashr_by_0(i41 %A) {
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; CHECK-LABEL: @ashr_by_0(
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; CHECK-NEXT: ret i41 [[A:%.*]]
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;
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%B = ashr i41 %A, 0
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ret i41 %B
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}
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define i39 @ashr_0(i39 %X) {
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; CHECK-LABEL: @ashr_0(
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; CHECK-NEXT: ret i39 0
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;
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%B = ashr i39 0, %X
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ret i39 %B
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}
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define <2 x i141> @ashr_0_vec_undef_elt(<2 x i141> %X) {
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; CHECK-LABEL: @ashr_0_vec_undef_elt(
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; CHECK-NEXT: ret <2 x i141> zeroinitializer
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;
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%B = shl <2 x i141> <i141 undef, i141 0>, %X
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ret <2 x i141> %B
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}
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define i55 @lshr_by_bitwidth(i55 %A) {
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; CHECK-LABEL: @lshr_by_bitwidth(
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; CHECK-NEXT: ret i55 undef
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;
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%B = lshr i55 %A, 55
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ret i55 %B
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}
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define i32 @shl_by_bitwidth(i32 %A) {
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; CHECK-LABEL: @shl_by_bitwidth(
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; CHECK-NEXT: ret i32 undef
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;
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%B = shl i32 %A, 32
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ret i32 %B
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}
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define <4 x i32> @lshr_by_bitwidth_splat(<4 x i32> %A) {
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; CHECK-LABEL: @lshr_by_bitwidth_splat(
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; CHECK-NEXT: ret <4 x i32> undef
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;
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%B = lshr <4 x i32> %A, <i32 32, i32 32, i32 32, i32 32> ;; shift all bits out
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ret <4 x i32> %B
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}
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define <4 x i32> @lshr_by_0_splat(<4 x i32> %A) {
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; CHECK-LABEL: @lshr_by_0_splat(
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; CHECK-NEXT: ret <4 x i32> [[A:%.*]]
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;
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%B = lshr <4 x i32> %A, zeroinitializer
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ret <4 x i32> %B
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}
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define <4 x i32> @shl_by_bitwidth_splat(<4 x i32> %A) {
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; CHECK-LABEL: @shl_by_bitwidth_splat(
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; CHECK-NEXT: ret <4 x i32> undef
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;
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%B = shl <4 x i32> %A, <i32 32, i32 32, i32 32, i32 32> ;; shift all bits out
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ret <4 x i32> %B
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}
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define i32 @ashr_undef() {
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; CHECK-LABEL: @ashr_undef(
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; CHECK-NEXT: ret i32 0
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;
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%B = ashr i32 undef, 2 ;; top two bits must be equal, so not undef
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ret i32 %B
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}
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define i32 @ashr_undef_variable_shift_amount(i32 %A) {
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; CHECK-LABEL: @ashr_undef_variable_shift_amount(
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; CHECK-NEXT: ret i32 0
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;
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%B = ashr i32 undef, %A ;; top %A bits must be equal, so not undef
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ret i32 %B
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}
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define i32 @ashr_all_ones(i32 %A) {
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; CHECK-LABEL: @ashr_all_ones(
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; CHECK-NEXT: ret i32 -1
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;
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%B = ashr i32 -1, %A
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ret i32 %B
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}
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define <3 x i8> @ashr_all_ones_vec_with_undef_elts(<3 x i8> %x, <3 x i8> %y) {
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; CHECK-LABEL: @ashr_all_ones_vec_with_undef_elts(
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; CHECK-NEXT: ret <3 x i8> <i8 -1, i8 -1, i8 -1>
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;
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%sh = ashr <3 x i8> <i8 undef, i8 -1, i8 undef>, %y
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ret <3 x i8> %sh
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}
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define i8 @lshr_by_sext_bool(i1 %x, i8 %y) {
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; CHECK-LABEL: @lshr_by_sext_bool(
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; CHECK-NEXT: ret i8 [[Y:%.*]]
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;
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%s = sext i1 %x to i8
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%r = lshr i8 %y, %s
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ret i8 %r
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}
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define <2 x i8> @lshr_by_sext_bool_vec(<2 x i1> %x, <2 x i8> %y) {
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; CHECK-LABEL: @lshr_by_sext_bool_vec(
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; CHECK-NEXT: ret <2 x i8> [[Y:%.*]]
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;
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%s = sext <2 x i1> %x to <2 x i8>
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%r = lshr <2 x i8> %y, %s
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ret <2 x i8> %r
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}
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define i8 @ashr_by_sext_bool(i1 %x, i8 %y) {
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; CHECK-LABEL: @ashr_by_sext_bool(
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; CHECK-NEXT: ret i8 [[Y:%.*]]
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;
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%s = sext i1 %x to i8
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%r = ashr i8 %y, %s
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ret i8 %r
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}
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define <2 x i8> @ashr_by_sext_bool_vec(<2 x i1> %x, <2 x i8> %y) {
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; CHECK-LABEL: @ashr_by_sext_bool_vec(
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; CHECK-NEXT: ret <2 x i8> [[Y:%.*]]
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;
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%s = sext <2 x i1> %x to <2 x i8>
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%r = ashr <2 x i8> %y, %s
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ret <2 x i8> %r
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}
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define i8 @shl_by_sext_bool(i1 %x, i8 %y) {
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; CHECK-LABEL: @shl_by_sext_bool(
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; CHECK-NEXT: ret i8 [[Y:%.*]]
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;
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%s = sext i1 %x to i8
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%r = shl i8 %y, %s
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ret i8 %r
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}
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define <2 x i8> @shl_by_sext_bool_vec(<2 x i1> %x, <2 x i8> %y) {
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; CHECK-LABEL: @shl_by_sext_bool_vec(
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; CHECK-NEXT: ret <2 x i8> [[Y:%.*]]
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;
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%s = sext <2 x i1> %x to <2 x i8>
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%r = shl <2 x i8> %y, %s
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ret <2 x i8> %r
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}
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define i64 @shl_or_shr(i32 %a, i32 %b) {
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; CHECK-LABEL: @shl_or_shr(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64
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; CHECK-NEXT: ret i64 [[TMP1]]
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;
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%tmp1 = zext i32 %a to i64
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%tmp2 = zext i32 %b to i64
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%tmp3 = shl nuw i64 %tmp1, 32
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%tmp4 = or i64 %tmp2, %tmp3
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%tmp5 = lshr i64 %tmp4, 32
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ret i64 %tmp5
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}
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; Since shift count of shl is smaller than the size of %b, OR cannot be eliminated.
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define i64 @shl_or_shr2(i32 %a, i32 %b) {
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; CHECK-LABEL: @shl_or_shr2(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64
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; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 31
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; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 31
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; CHECK-NEXT: ret i64 [[TMP5]]
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;
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%tmp1 = zext i32 %a to i64
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%tmp2 = zext i32 %b to i64
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%tmp3 = shl nuw i64 %tmp1, 31
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%tmp4 = or i64 %tmp2, %tmp3
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%tmp5 = lshr i64 %tmp4, 31
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ret i64 %tmp5
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}
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; Unit test for vector integer
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define <2 x i64> @shl_or_shr1v(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: @shl_or_shr1v(
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; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64>
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; CHECK-NEXT: ret <2 x i64> [[TMP1]]
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;
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%tmp1 = zext <2 x i32> %a to <2 x i64>
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%tmp2 = zext <2 x i32> %b to <2 x i64>
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%tmp3 = shl nuw <2 x i64> %tmp1, <i64 32, i64 32>
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%tmp4 = or <2 x i64> %tmp3, %tmp2
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%tmp5 = lshr <2 x i64> %tmp4, <i64 32, i64 32>
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ret <2 x i64> %tmp5
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}
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; Negative unit test for vector integer
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define <2 x i64> @shl_or_shr2v(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: @shl_or_shr2v(
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; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64>
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; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[B:%.*]] to <2 x i64>
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i64> [[TMP1]], <i64 31, i64 31>
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; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i64> [[TMP2]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = lshr <2 x i64> [[TMP4]], <i64 31, i64 31>
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; CHECK-NEXT: ret <2 x i64> [[TMP5]]
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;
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%tmp1 = zext <2 x i32> %a to <2 x i64>
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%tmp2 = zext <2 x i32> %b to <2 x i64>
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%tmp3 = shl nuw <2 x i64> %tmp1, <i64 31, i64 31>
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%tmp4 = or <2 x i64> %tmp2, %tmp3
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%tmp5 = lshr <2 x i64> %tmp4, <i64 31, i64 31>
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ret <2 x i64> %tmp5
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}
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