forked from OSchip/llvm-project
191 lines
5.3 KiB
LLVM
191 lines
5.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instsimplify -S | FileCheck %s
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; If any bits of the shift amount are known to make it exceed or equal
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; the number of bits in the type, the shift causes undefined behavior.
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define i32 @shl_amount_is_known_bogus(i32 %a, i32 %b) {
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; CHECK-LABEL: @shl_amount_is_known_bogus(
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; CHECK-NEXT: ret i32 undef
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;
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%or = or i32 %b, 32
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%shl = shl i32 %a, %or
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ret i32 %shl
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}
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; Check some weird types and the other shift ops.
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define i31 @lshr_amount_is_known_bogus(i31 %a, i31 %b) {
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; CHECK-LABEL: @lshr_amount_is_known_bogus(
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; CHECK-NEXT: ret i31 undef
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;
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%or = or i31 %b, 31
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%shr = lshr i31 %a, %or
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ret i31 %shr
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}
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define i33 @ashr_amount_is_known_bogus(i33 %a, i33 %b) {
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; CHECK-LABEL: @ashr_amount_is_known_bogus(
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; CHECK-NEXT: ret i33 undef
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;
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%or = or i33 %b, 33
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%shr = ashr i33 %a, %or
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ret i33 %shr
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}
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; If all valid bits of the shift amount are known 0, there's no shift.
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; It doesn't matter if high bits are set because that would be undefined.
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; Therefore, the only possible valid result of these shifts is %a.
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define i16 @ashr_amount_is_zero(i16 %a, i16 %b) {
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; CHECK-LABEL: @ashr_amount_is_zero(
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; CHECK-NEXT: ret i16 %a
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;
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%and = and i16 %b, 65520 ; 0xfff0
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%shr = ashr i16 %a, %and
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ret i16 %shr
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}
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define i300 @lshr_amount_is_zero(i300 %a, i300 %b) {
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; CHECK-LABEL: @lshr_amount_is_zero(
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; CHECK-NEXT: ret i300 %a
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;
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%and = and i300 %b, 2048
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%shr = lshr i300 %a, %and
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ret i300 %shr
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}
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define i9 @shl_amount_is_zero(i9 %a, i9 %b) {
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; CHECK-LABEL: @shl_amount_is_zero(
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; CHECK-NEXT: ret i9 %a
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;
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%and = and i9 %b, 496 ; 0x1f0
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%shl = shl i9 %a, %and
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ret i9 %shl
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}
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; Verify that we've calculated the log2 boundary of valid bits correctly for a weird type.
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define i9 @shl_amount_is_not_known_zero(i9 %a, i9 %b) {
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; CHECK-LABEL: @shl_amount_is_not_known_zero(
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; CHECK-NEXT: [[AND:%.*]] = and i9 %b, -8
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; CHECK-NEXT: [[SHL:%.*]] = shl i9 %a, [[AND]]
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; CHECK-NEXT: ret i9 [[SHL]]
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;
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%and = and i9 %b, 504 ; 0x1f8
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%shl = shl i9 %a, %and
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ret i9 %shl
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}
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; For vectors, we need all scalar elements to meet the requirements to optimize.
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define <2 x i32> @ashr_vector_bogus(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: @ashr_vector_bogus(
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; CHECK-NEXT: ret <2 x i32> undef
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;
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%or = or <2 x i32> %b, <i32 32, i32 32>
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%shr = ashr <2 x i32> %a, %or
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ret <2 x i32> %shr
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}
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; FIXME: This is undef, but computeKnownBits doesn't handle the union.
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define <2 x i32> @shl_vector_bogus(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: @shl_vector_bogus(
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; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> %b, <i32 32, i32 64>
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; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> %a, [[OR]]
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; CHECK-NEXT: ret <2 x i32> [[SHL]]
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;
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%or = or <2 x i32> %b, <i32 32, i32 64>
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%shl = shl <2 x i32> %a, %or
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ret <2 x i32> %shl
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}
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define <2 x i32> @lshr_vector_zero(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: @lshr_vector_zero(
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; CHECK-NEXT: ret <2 x i32> %a
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;
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%and = and <2 x i32> %b, <i32 64, i32 256>
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%shr = lshr <2 x i32> %a, %and
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ret <2 x i32> %shr
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}
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; Make sure that weird vector types work too.
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define <2 x i15> @shl_vector_zero(<2 x i15> %a, <2 x i15> %b) {
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; CHECK-LABEL: @shl_vector_zero(
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; CHECK-NEXT: ret <2 x i15> %a
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;
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%and = and <2 x i15> %b, <i15 1024, i15 1024>
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%shl = shl <2 x i15> %a, %and
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ret <2 x i15> %shl
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}
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define <2 x i32> @shl_vector_for_real(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: @shl_vector_for_real(
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; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> %b, <i32 3, i32 3>
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; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> %a, [[AND]]
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; CHECK-NEXT: ret <2 x i32> [[SHL]]
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;
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%and = and <2 x i32> %b, <i32 3, i32 3> ; a necessary mask op
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%shl = shl <2 x i32> %a, %and
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ret <2 x i32> %shl
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}
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; We calculate the valid bits of the shift using log2, and log2 of 1 (the type width) is 0.
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; That should be ok. Either the shift amount is 0 or invalid (1), so we can always return %a.
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define i1 @shl_i1(i1 %a, i1 %b) {
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; CHECK-LABEL: @shl_i1(
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; CHECK-NEXT: ret i1 %a
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;
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%shl = shl i1 %a, %b
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ret i1 %shl
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}
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; Simplify count leading/trailing zeros to zero if all valid bits are shifted out.
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declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone
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declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
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declare <2 x i8> @llvm.cttz.v2i8(<2 x i8>, i1) nounwind readnone
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declare <2 x i8> @llvm.ctlz.v2i8(<2 x i8>, i1) nounwind readnone
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define i32 @lshr_ctlz_zero_is_undef(i32 %x) {
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; CHECK-LABEL: @lshr_ctlz_zero_is_undef(
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; CHECK-NEXT: ret i32 0
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;
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%ct = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
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%sh = lshr i32 %ct, 5
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ret i32 %sh
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}
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define i32 @lshr_cttz_zero_is_undef(i32 %x) {
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; CHECK-LABEL: @lshr_cttz_zero_is_undef(
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; CHECK-NEXT: ret i32 0
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;
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%ct = call i32 @llvm.cttz.i32(i32 %x, i1 true)
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%sh = lshr i32 %ct, 5
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ret i32 %sh
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}
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define <2 x i8> @lshr_ctlz_zero_is_undef_splat_vec(<2 x i8> %x) {
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; CHECK-LABEL: @lshr_ctlz_zero_is_undef_splat_vec(
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; CHECK-NEXT: ret <2 x i8> zeroinitializer
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;
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%ct = call <2 x i8> @llvm.ctlz.v2i8(<2 x i8> %x, i1 true)
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%sh = lshr <2 x i8> %ct, <i8 3, i8 3>
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ret <2 x i8> %sh
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}
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define <2 x i8> @lshr_cttz_zero_is_undef_splat_vec(<2 x i8> %x) {
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; CHECK-LABEL: @lshr_cttz_zero_is_undef_splat_vec(
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; CHECK-NEXT: ret <2 x i8> zeroinitializer
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;
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%ct = call <2 x i8> @llvm.cttz.v2i8(<2 x i8> %x, i1 true)
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%sh = lshr <2 x i8> %ct, <i8 3, i8 3>
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ret <2 x i8> %sh
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}
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