Simon Pilgrim 180639afe5 [SelectionDAG] Initial support for FSHL/FSHR funnel shift opcodes (PR39467) ... This is an initial patch to add a minimum level of support for funnel shifts to the SelectionDAG and to begin wiring it up to the X86 SHLD/SHRD instructions. Some partial legalization code has been added to handle the case for 'SlowSHLD' where we want to expand instead and I've added a few DAG combines so we don't get regressions from the existing DAG builder expansion code. Differential Revision: https://reviews.llvm.org/D54698 llvm-svn: 348353		2018-12-05 11:12:12 +00:00
..
AArch64	AArch64: support funclets in fastcall and swift_call	2018-12-05 07:09:20 +00:00
AMDGPU	[MachineLICM][X86][AMDGPU] Fix subtle bug in the updating of PhysRegClobbers in post-RA LICM	2018-12-05 03:41:26 +00:00
ARC	…
ARM	[ARM GlobalISel] Implement call lowering for Thumb2	2018-12-05 10:35:28 +00:00
AVR	[AVR] Reorder the CHECK lines in directmem.ll to match current trunk	2018-11-09 23:17:59 +00:00
BPF	…
Generic	Move llc-start-stop-instance to x86	2018-12-04 18:19:08 +00:00
Hexagon	[Hexagon] Switch to auto-generated intrinsic definitions and patterns	2018-12-03 22:40:36 +00:00
Inputs	…
Lanai	…
MIR	[CodeGen] Fix bugs in BranchFolderPass when debug labels are generated.	2018-11-30 08:07:29 +00:00
MSP430	[MSP430] Optimize srl/sra in case of A >> (8 + N)	2018-11-19 10:43:02 +00:00
Mips	[TargetLowering] expandFP_TO_UINT - improve fp16 support	2018-11-19 19:16:13 +00:00
NVPTX	[NVPTX] Add lowering of i128 numbers as struct fields	2018-12-01 00:21:52 +00:00
Nios2	…
PowerPC	[PowerPC] Make no-PIC default to match GCC - LLVM	2018-12-04 20:14:57 +00:00
RISCV	[RISCV] Remove RV64I SLLW/SRLW/SRAW patterns and add new test cases	2018-12-01 05:00:00 +00:00
SPARC	Relax fast register allocator related test cases; NFC	2018-10-29 20:10:42 +00:00
SystemZ	[SystemZ] make test immune to improvements in undef simplification	2018-11-18 16:50:44 +00:00
Thumb	[SelectionDAG] swap select_cc operands to enable folding	2018-11-09 11:09:40 +00:00
Thumb2	[ARM] Enable spilling of the hGPR register class in Thumb2	2018-11-08 13:02:10 +00:00
WebAssembly	[WebAssembly] WebAssemblyLowerEmscriptenEHSjLj: use getter/setter for accessing tempRet0	2018-11-20 19:25:07 +00:00
WinCFGuard	…
WinEH	…
X86	[SelectionDAG] Initial support for FSHL/FSHR funnel shift opcodes (PR39467)	2018-12-05 11:12:12 +00:00
XCore	Relax fast register allocator related test cases; NFC	2018-10-29 20:10:42 +00:00