forked from OSchip/llvm-project
52 lines
2.3 KiB
C
52 lines
2.3 KiB
C
// RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs -mfloat-abi soft -fallow-half-arguments-and-returns -emit-llvm -o - -O1 %s | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT
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// RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs -mfloat-abi hard -fallow-half-arguments-and-returns -emit-llvm -o - -O1 %s | FileCheck %s --check-prefix=CHECK --check-prefix=HARD
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// RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs -mfloat-abi soft -fnative-half-arguments-and-returns -emit-llvm -o - -O1 %s | FileCheck %s --check-prefix=NATIVE
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__fp16 g;
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void t1(__fp16 a) { g = a; }
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// SOFT: define void @t1(i32 [[PARAM:%.*]])
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// SOFT: [[TRUNC:%.*]] = trunc i32 [[PARAM]] to i16
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// HARD: define arm_aapcs_vfpcc void @t1(float [[PARAM:%.*]])
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// HARD: [[BITCAST:%.*]] = bitcast float [[PARAM]] to i32
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// HARD: [[TRUNC:%.*]] = trunc i32 [[BITCAST]] to i16
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// CHECK: store i16 [[TRUNC]], i16* bitcast (half* @g to i16*)
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// NATIVE: define void @t1(half [[PARAM:%.*]])
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// NATIVE: store half [[PARAM]], half* @g
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__fp16 t2() { return g; }
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// SOFT: define i32 @t2()
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// HARD: define arm_aapcs_vfpcc float @t2()
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// NATIVE: define half @t2()
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// CHECK: [[LOAD:%.*]] = load i16, i16* bitcast (half* @g to i16*)
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// CHECK: [[ZEXT:%.*]] = zext i16 [[LOAD]] to i32
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// SOFT: ret i32 [[ZEXT]]
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// HARD: [[BITCAST:%.*]] = bitcast i32 [[ZEXT]] to float
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// HARD: ret float [[BITCAST]]
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// NATIVE: [[LOAD:%.*]] = load half, half* @g
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// NATIVE: ret half [[LOAD]]
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_Float16 h;
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void t3(_Float16 a) { h = a; }
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// SOFT: define void @t3(i32 [[PARAM:%.*]])
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// SOFT: [[TRUNC:%.*]] = trunc i32 [[PARAM]] to i16
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// HARD: define arm_aapcs_vfpcc void @t3(float [[PARAM:%.*]])
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// HARD: [[BITCAST:%.*]] = bitcast float [[PARAM]] to i32
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// HARD: [[TRUNC:%.*]] = trunc i32 [[BITCAST]] to i16
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// CHECK: store i16 [[TRUNC]], i16* bitcast (half* @h to i16*)
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// NATIVE: define void @t3(half [[PARAM:%.*]])
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// NATIVE: store half [[PARAM]], half* @h
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_Float16 t4() { return h; }
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// SOFT: define i32 @t4()
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// HARD: define arm_aapcs_vfpcc float @t4()
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// NATIVE: define half @t4()
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// CHECK: [[LOAD:%.*]] = load i16, i16* bitcast (half* @h to i16*)
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// CHECK: [[ZEXT:%.*]] = zext i16 [[LOAD]] to i32
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// SOFT: ret i32 [[ZEXT]]
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// HARD: [[BITCAST:%.*]] = bitcast i32 [[ZEXT]] to float
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// HARD: ret float [[BITCAST]]
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// NATIVE: [[LOAD:%.*]] = load half, half* @h
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// NATIVE: ret half [[LOAD]]
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