forked from OSchip/llvm-project
251 lines
9.8 KiB
C++
251 lines
9.8 KiB
C++
//===- SPIRVModuleAnalysis.cpp - analysis of global instrs & regs - C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// The analysis collects instructions that should be output at the module level
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// and performs the global register numbering.
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//
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// The results of this analysis are used in AsmPrinter to rename registers
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// globally and to output required instructions at the module level.
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//
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//===----------------------------------------------------------------------===//
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#include "SPIRVModuleAnalysis.h"
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#include "SPIRV.h"
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#include "SPIRVGlobalRegistry.h"
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#include "SPIRVSubtarget.h"
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#include "SPIRVTargetMachine.h"
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#include "SPIRVUtils.h"
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#include "TargetInfo/SPIRVTargetInfo.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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using namespace llvm;
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#define DEBUG_TYPE "spirv-module-analysis"
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char llvm::SPIRVModuleAnalysis::ID = 0;
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namespace llvm {
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void initializeSPIRVModuleAnalysisPass(PassRegistry &);
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} // namespace llvm
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INITIALIZE_PASS(SPIRVModuleAnalysis, DEBUG_TYPE, "SPIRV module analysis", true,
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true)
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// Retrieve an unsigned from an MDNode with a list of them as operands.
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static unsigned getMetadataUInt(MDNode *MdNode, unsigned OpIndex,
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unsigned DefaultVal = 0) {
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if (MdNode && OpIndex < MdNode->getNumOperands()) {
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const auto &Op = MdNode->getOperand(OpIndex);
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return mdconst::extract<ConstantInt>(Op)->getZExtValue();
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}
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return DefaultVal;
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}
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void SPIRVModuleAnalysis::setBaseInfo(const Module &M) {
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MAI.MaxID = 0;
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for (int i = 0; i < SPIRV::NUM_MODULE_SECTIONS; i++)
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MAI.MS[i].clear();
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MAI.RegisterAliasTable.clear();
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MAI.InstrsToDelete.clear();
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MAI.FuncNameMap.clear();
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MAI.GlobalVarList.clear();
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// TODO: determine memory model and source language from the configuratoin.
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MAI.Mem = SPIRV::MemoryModel::OpenCL;
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MAI.SrcLang = SPIRV::SourceLanguage::OpenCL_C;
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unsigned PtrSize = ST->getPointerSize();
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MAI.Addr = PtrSize == 32 ? SPIRV::AddressingModel::Physical32
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: PtrSize == 64 ? SPIRV::AddressingModel::Physical64
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: SPIRV::AddressingModel::Logical;
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// Get the OpenCL version number from metadata.
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// TODO: support other source languages.
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MAI.SrcLangVersion = 0;
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if (auto VerNode = M.getNamedMetadata("opencl.ocl.version")) {
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// Construct version literal according to OpenCL 2.2 environment spec.
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auto VersionMD = VerNode->getOperand(0);
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unsigned MajorNum = getMetadataUInt(VersionMD, 0, 2);
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unsigned MinorNum = getMetadataUInt(VersionMD, 1);
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unsigned RevNum = getMetadataUInt(VersionMD, 2);
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MAI.SrcLangVersion = 0 | (MajorNum << 16) | (MinorNum << 8) | RevNum;
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}
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}
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// True if there is an instruction in the MS list with all the same operands as
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// the given instruction has (after the given starting index).
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// TODO: maybe it needs to check Opcodes too.
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static bool findSameInstrInMS(const MachineInstr &A,
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SPIRV::ModuleSectionType MSType,
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SPIRV::ModuleAnalysisInfo &MAI,
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bool UpdateRegAliases,
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unsigned StartOpIndex = 0) {
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for (const auto *B : MAI.MS[MSType]) {
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const unsigned NumAOps = A.getNumOperands();
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if (NumAOps == B->getNumOperands() && A.getNumDefs() == B->getNumDefs()) {
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bool AllOpsMatch = true;
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for (unsigned i = StartOpIndex; i < NumAOps && AllOpsMatch; ++i) {
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if (A.getOperand(i).isReg() && B->getOperand(i).isReg()) {
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Register RegA = A.getOperand(i).getReg();
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Register RegB = B->getOperand(i).getReg();
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AllOpsMatch = MAI.getRegisterAlias(A.getMF(), RegA) ==
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MAI.getRegisterAlias(B->getMF(), RegB);
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} else {
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AllOpsMatch = A.getOperand(i).isIdenticalTo(B->getOperand(i));
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}
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}
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if (AllOpsMatch) {
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if (UpdateRegAliases) {
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assert(A.getOperand(0).isReg() && B->getOperand(0).isReg());
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Register LocalReg = A.getOperand(0).getReg();
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Register GlobalReg =
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MAI.getRegisterAlias(B->getMF(), B->getOperand(0).getReg());
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MAI.setRegisterAlias(A.getMF(), LocalReg, GlobalReg);
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}
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return true;
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}
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}
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}
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return false;
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}
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// Look for IDs declared with Import linkage, and map the imported name string
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// to the register defining that variable (which will usually be the result of
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// an OpFunction). This lets us call externally imported functions using
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// the correct ID registers.
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void SPIRVModuleAnalysis::collectFuncNames(MachineInstr &MI,
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const Function &F) {
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if (MI.getOpcode() == SPIRV::OpDecorate) {
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// If it's got Import linkage.
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auto Dec = MI.getOperand(1).getImm();
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if (Dec == static_cast<unsigned>(SPIRV::Decoration::LinkageAttributes)) {
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auto Lnk = MI.getOperand(MI.getNumOperands() - 1).getImm();
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if (Lnk == static_cast<unsigned>(SPIRV::LinkageType::Import)) {
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// Map imported function name to function ID register.
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std::string Name = getStringImm(MI, 2);
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Register Target = MI.getOperand(0).getReg();
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// TODO: check defs from different MFs.
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MAI.FuncNameMap[Name] = MAI.getRegisterAlias(MI.getMF(), Target);
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}
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}
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} else if (MI.getOpcode() == SPIRV::OpFunction) {
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// Record all internal OpFunction declarations.
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Register Reg = MI.defs().begin()->getReg();
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Register GlobalReg = MAI.getRegisterAlias(MI.getMF(), Reg);
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assert(GlobalReg.isValid());
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// TODO: check that it does not conflict with existing entries.
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MAI.FuncNameMap[F.getGlobalIdentifier()] = GlobalReg;
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}
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}
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// Collect the given instruction in the specified MS. We assume global register
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// numbering has already occurred by this point. We can directly compare reg
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// arguments when detecting duplicates.
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static void collectOtherInstr(MachineInstr &MI, SPIRV::ModuleAnalysisInfo &MAI,
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SPIRV::ModuleSectionType MSType,
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bool IsConstOrType = false) {
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MAI.setSkipEmission(&MI);
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if (findSameInstrInMS(MI, MSType, MAI, IsConstOrType, IsConstOrType ? 1 : 0))
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return; // Found a duplicate, so don't add it.
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// No duplicates, so add it.
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MAI.MS[MSType].push_back(&MI);
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}
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// Some global instructions make reference to function-local ID regs, so cannot
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// be correctly collected until these registers are globally numbered.
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void SPIRVModuleAnalysis::processOtherInstrs(const Module &M) {
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for (auto F = M.begin(), E = M.end(); F != E; ++F) {
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if ((*F).isDeclaration())
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continue;
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MachineFunction *MF = MMI->getMachineFunction(*F);
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assert(MF);
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unsigned FCounter = 0;
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for (MachineBasicBlock &MBB : *MF)
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for (MachineInstr &MI : MBB) {
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if (MI.getOpcode() == SPIRV::OpFunction)
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FCounter++;
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if (MAI.getSkipEmission(&MI))
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continue;
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const unsigned OpCode = MI.getOpcode();
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const bool IsFuncOrParm =
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OpCode == SPIRV::OpFunction || OpCode == SPIRV::OpFunctionParameter;
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const bool IsConstOrType =
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TII->isConstantInstr(MI) || TII->isTypeDeclInstr(MI);
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if (OpCode == SPIRV::OpName || OpCode == SPIRV::OpMemberName) {
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collectOtherInstr(MI, MAI, SPIRV::MB_DebugNames);
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} else if (OpCode == SPIRV::OpEntryPoint) {
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collectOtherInstr(MI, MAI, SPIRV::MB_EntryPoints);
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} else if (TII->isDecorationInstr(MI)) {
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collectOtherInstr(MI, MAI, SPIRV::MB_Annotations);
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collectFuncNames(MI, *F);
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} else if (IsConstOrType || (FCounter > 1 && IsFuncOrParm)) {
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// Now OpSpecConstant*s are not in DT,
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// but they need to be collected anyway.
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enum SPIRV::ModuleSectionType Type =
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IsFuncOrParm ? SPIRV::MB_ExtFuncDecls : SPIRV::MB_TypeConstVars;
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collectOtherInstr(MI, MAI, Type, IsConstOrType);
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} else if (OpCode == SPIRV::OpFunction) {
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collectFuncNames(MI, *F);
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}
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}
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}
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}
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// Number registers in all functions globally from 0 onwards and store
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// the result in global register alias table.
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void SPIRVModuleAnalysis::numberRegistersGlobally(const Module &M) {
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for (auto F = M.begin(), E = M.end(); F != E; ++F) {
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if ((*F).isDeclaration())
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continue;
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MachineFunction *MF = MMI->getMachineFunction(*F);
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assert(MF);
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for (MachineBasicBlock &MBB : *MF) {
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for (MachineInstr &MI : MBB) {
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for (MachineOperand &Op : MI.operands()) {
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if (!Op.isReg())
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continue;
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Register Reg = Op.getReg();
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if (MAI.hasRegisterAlias(MF, Reg))
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continue;
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Register NewReg = Register::index2VirtReg(MAI.getNextID());
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MAI.setRegisterAlias(MF, Reg, NewReg);
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}
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}
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}
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}
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}
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struct SPIRV::ModuleAnalysisInfo SPIRVModuleAnalysis::MAI;
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void SPIRVModuleAnalysis::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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AU.addRequired<MachineModuleInfoWrapperPass>();
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}
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bool SPIRVModuleAnalysis::runOnModule(Module &M) {
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SPIRVTargetMachine &TM =
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getAnalysis<TargetPassConfig>().getTM<SPIRVTargetMachine>();
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ST = TM.getSubtargetImpl();
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GR = ST->getSPIRVGlobalRegistry();
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TII = ST->getInstrInfo();
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MMI = &getAnalysis<MachineModuleInfoWrapperPass>().getMMI();
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setBaseInfo(M);
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// TODO: Process type/const/global var/func decl instructions, number their
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// destination registers from 0 to N, collect Extensions and Capabilities.
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// Number rest of registers from N+1 onwards.
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numberRegistersGlobally(M);
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// Collect OpName, OpEntryPoint, OpDecorate etc, process other instructions.
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processOtherInstrs(M);
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return false;
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}
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